Lines Matching defs:adev
36 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
38 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) &&
39 adev->gmc.xgmi.connected_to_cpu))
50 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
53 dev_dbg(adev->dev, "Getting reset handler for method %d\n",
72 dev_dbg(adev->dev, "Reset handler not found!\n");
77 static int aldebaran_mode2_suspend_ip(struct amdgpu_device *adev)
81 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
82 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
84 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
85 if (!(adev->ip_blocks[i].version->type ==
87 adev->ip_blocks[i].version->type ==
91 r = adev->ip_blocks[i].version->funcs->suspend(adev);
94 dev_err(adev->dev,
96 adev->ip_blocks[i].version->funcs->name, r);
100 adev->ip_blocks[i].status.hw = false;
111 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
113 dev_dbg(adev->dev, "Aldebaran prepare hw context\n");
115 if (!amdgpu_sriov_vf(adev))
116 r = aldebaran_mode2_suspend_ip(adev);
126 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
131 dev_dbg(adev->dev, "Resetting device\n");
132 handler->do_reset(adev);
138 static int aldebaran_mode2_reset(struct amdgpu_device *adev)
141 pci_clear_master(adev->pdev);
142 adev->asic_reset_res = amdgpu_dpm_mode2_reset(adev);
143 return adev->asic_reset_res;
150 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
155 dev_dbg(adev->dev, "aldebaran perform hw reset\n");
160 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) &&
210 static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev)
218 dev_dbg(adev->dev, "Reloading ucodes after reset\n");
219 for (i = 0; i < adev->firmware.max_ucodes; i++) {
220 ucode = &adev->firmware.ucode[i];
247 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_COMMON);
249 dev_err(adev->dev, "Failed to get BIF handle\n");
252 r = cmn_block->version->funcs->resume(adev);
257 adev->gfxhub.funcs->init(adev);
258 r = adev->gfxhub.funcs->gart_enable(adev);
260 dev_err(adev->dev, "GFXHUB gart reenable failed after reset\n");
265 r = psp_load_fw_list(&adev->psp, ucode_list, ucode_count);
267 dev_err(adev->dev, "GFX ucode load failed after reset\n");
272 adev->gfx.rlc.funcs->resume(adev);
275 r = amdgpu_dpm_wait_for_event(adev, SMU_EVENT_RESET_COMPLETE, 0);
277 dev_err(adev->dev,
282 for (i = 0; i < adev->num_ip_blocks; i++) {
283 if (!(adev->ip_blocks[i].version->type ==
285 adev->ip_blocks[i].version->type ==
288 r = adev->ip_blocks[i].version->funcs->resume(adev);
290 dev_err(adev->dev,
292 adev->ip_blocks[i].version->funcs->name, r);
296 adev->ip_blocks[i].status.hw = true;
299 for (i = 0; i < adev->num_ip_blocks; i++) {
300 if (!(adev->ip_blocks[i].version->type ==
302 adev->ip_blocks[i].version->type ==
304 adev->ip_blocks[i].version->type ==
308 if (adev->ip_blocks[i].version->funcs->late_init) {
309 r = adev->ip_blocks[i].version->funcs->late_init(
310 (void *)adev);
312 dev_err(adev->dev,
314 adev->ip_blocks[i].version->funcs->name,
319 adev->ip_blocks[i].status.late_initialized = true;
322 amdgpu_ras_set_error_query_ready(adev, true);
324 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
325 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
422 int aldebaran_reset_init(struct amdgpu_device *adev)
430 reset_ctl->handle = adev;
440 adev->reset_cntl = reset_ctl;
445 int aldebaran_reset_fini(struct amdgpu_device *adev)
447 kfree(adev->reset_cntl);
448 adev->reset_cntl = NULL;