Lines Matching defs:wg
127 static void wcove_update_irq_mask(struct wcove_gpio *wg, irq_hw_number_t gpio)
131 if (wg->set_irq_mask)
132 regmap_set_bits(wg->regmap, reg, mask);
134 regmap_clear_bits(wg->regmap, reg, mask);
137 static void wcove_update_irq_ctrl(struct wcove_gpio *wg, irq_hw_number_t gpio)
141 regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt);
146 struct wcove_gpio *wg = gpiochip_get_data(chip);
152 return regmap_write(wg->regmap, reg, CTLO_INPUT_SET);
158 struct wcove_gpio *wg = gpiochip_get_data(chip);
164 return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET | value);
169 struct wcove_gpio *wg = gpiochip_get_data(chip);
176 ret = regmap_read(wg->regmap, reg, &val);
188 struct wcove_gpio *wg = gpiochip_get_data(chip);
195 ret = regmap_read(wg->regmap, reg, &val);
204 struct wcove_gpio *wg = gpiochip_get_data(chip);
211 regmap_set_bits(wg->regmap, reg, 1);
213 regmap_clear_bits(wg->regmap, reg, 1);
219 struct wcove_gpio *wg = gpiochip_get_data(chip);
227 return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
230 return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
242 struct wcove_gpio *wg = gpiochip_get_data(chip);
250 wg->intcnt = CTLI_INTCNT_DIS;
253 wg->intcnt = CTLI_INTCNT_BE;
256 wg->intcnt = CTLI_INTCNT_PE;
259 wg->intcnt = CTLI_INTCNT_NE;
265 wg->update |= UPDATE_IRQ_TYPE;
273 struct wcove_gpio *wg = gpiochip_get_data(chip);
275 mutex_lock(&wg->buslock);
281 struct wcove_gpio *wg = gpiochip_get_data(chip);
284 if (wg->update & UPDATE_IRQ_TYPE)
285 wcove_update_irq_ctrl(wg, gpio);
286 if (wg->update & UPDATE_IRQ_MASK)
287 wcove_update_irq_mask(wg, gpio);
288 wg->update = 0;
290 mutex_unlock(&wg->buslock);
296 struct wcove_gpio *wg = gpiochip_get_data(chip);
304 wg->set_irq_mask = false;
305 wg->update |= UPDATE_IRQ_MASK;
311 struct wcove_gpio *wg = gpiochip_get_data(chip);
317 wg->set_irq_mask = true;
318 wg->update |= UPDATE_IRQ_MASK;
336 struct wcove_gpio *wg = (struct wcove_gpio *)data;
341 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
342 dev_err(wg->dev, "Failed to read irq status register\n");
356 virq = irq_find_mapping(wg->chip.irq.domain, gpio);
358 regmap_set_bits(wg->regmap, reg, mask);
362 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
363 dev_err(wg->dev, "Failed to read irq status\n");
376 struct wcove_gpio *wg = gpiochip_get_data(chip);
380 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
381 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli);
383 dev_err(wg->dev, "Failed to read registers: CTRL out/in\n");
387 ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_MASK, &mask), &irq_mask);
388 ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_STATUS, &mask), &irq_status);
390 dev_err(wg->dev, "Failed to read registers: IRQ status/mask\n");
408 struct wcove_gpio *wg;
430 wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL);
431 if (!wg)
434 wg->regmap_irq_chip = pmic->irq_chip_data;
436 platform_set_drvdata(pdev, wg);
438 mutex_init(&wg->buslock);
439 wg->chip.label = KBUILD_MODNAME;
440 wg->chip.direction_input = wcove_gpio_dir_in;
441 wg->chip.direction_output = wcove_gpio_dir_out;
442 wg->chip.get_direction = wcove_gpio_get_direction;
443 wg->chip.get = wcove_gpio_get;
444 wg->chip.set = wcove_gpio_set;
445 wg->chip.set_config = wcove_gpio_set_config;
446 wg->chip.base = -1;
447 wg->chip.ngpio = WCOVE_VGPIO_NUM;
448 wg->chip.can_sleep = true;
449 wg->chip.parent = pdev->dev.parent;
450 wg->chip.dbg_show = wcove_gpio_dbg_show;
451 wg->dev = dev;
452 wg->regmap = pmic->regmap;
454 virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq);
460 girq = &wg->chip.irq;
471 IRQF_ONESHOT, pdev->name, wg);
477 ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
484 ret = regmap_clear_bits(wg->regmap, IRQ_MASK_BASE + 0, GPIO_IRQ0_MASK);
489 ret = regmap_clear_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK);