Lines Matching refs:bit_cfg
76 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
78 return (bit_cfg & GPIO_BIT_CFG_PIN_SEL_MASK) == 0;
135 u64 bit_cfg = txgpio->line_entries[line].fil_bits | GPIO_BIT_CFG_TX_OE;
145 bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
148 bit_cfg |= GPIO_BIT_CFG_TX_OD;
150 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
159 u64 bit_cfg;
169 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
171 if (bit_cfg & GPIO_BIT_CFG_TX_OE)
183 u64 bit_cfg;
199 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
236 bit_cfg &= ~GPIO_BIT_CFG_FIL_MASK;
237 bit_cfg |= txgpio->line_entries[line].fil_bits;
238 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
251 (bit_cfg & GPIO_BIT_CFG_TX_OE))
330 u64 bit_cfg;
334 bit_cfg = txline->fil_bits | GPIO_BIT_CFG_INT_EN;
338 bit_cfg |= GPIO_BIT_CFG_INT_TYPE;
345 bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
351 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line));
495 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(i));
505 txgpio->line_entries[i].fil_bits = bit_cfg ?
506 (bit_cfg & GPIO_BIT_CFG_FIL_MASK) : GLITCH_FILTER_400NS;
508 if ((bit_cfg & GPIO_BIT_CFG_TX_OE) && (bit_cfg & GPIO_BIT_CFG_TX_OD))
510 if (bit_cfg & GPIO_BIT_CFG_PIN_XOR)