Lines Matching defs:txgpio
47 struct thunderx_gpio *txgpio;
73 static bool thunderx_gpio_is_gpio_nowarn(struct thunderx_gpio *txgpio,
76 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
85 static bool thunderx_gpio_is_gpio(struct thunderx_gpio *txgpio,
88 bool rv = thunderx_gpio_is_gpio_nowarn(txgpio, line);
97 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
99 return thunderx_gpio_is_gpio(txgpio, line) ? 0 : -EIO;
104 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
106 if (!thunderx_gpio_is_gpio(txgpio, line))
109 raw_spin_lock(&txgpio->lock);
110 clear_bit(line, txgpio->invert_mask);
111 clear_bit(line, txgpio->od_mask);
112 writeq(txgpio->line_entries[line].fil_bits,
113 txgpio->register_base + bit_cfg_reg(line));
114 raw_spin_unlock(&txgpio->lock);
121 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
125 void __iomem *reg = txgpio->register_base +
134 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
135 u64 bit_cfg = txgpio->line_entries[line].fil_bits | GPIO_BIT_CFG_TX_OE;
137 if (!thunderx_gpio_is_gpio(txgpio, line))
140 raw_spin_lock(&txgpio->lock);
144 if (test_bit(line, txgpio->invert_mask))
147 if (test_bit(line, txgpio->od_mask))
150 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
152 raw_spin_unlock(&txgpio->lock);
158 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
161 if (!thunderx_gpio_is_gpio_nowarn(txgpio, line))
169 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
187 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
188 void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET;
190 if (!thunderx_gpio_is_gpio(txgpio, line))
193 raw_spin_lock(&txgpio->lock);
194 orig_invert = test_bit(line, txgpio->invert_mask);
196 orig_od = test_bit(line, txgpio->od_mask);
199 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
207 set_bit(line, txgpio->invert_mask);
209 set_bit(line, txgpio->od_mask);
214 clear_bit(line, txgpio->invert_mask);
216 clear_bit(line, txgpio->od_mask);
233 txgpio->line_entries[line].fil_bits =
237 bit_cfg |= txgpio->line_entries[line].fil_bits;
238 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
244 raw_spin_unlock(&txgpio->lock);
259 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
262 u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT);
265 if (test_bit(line, txgpio->invert_mask))
277 struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
282 writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET);
283 writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR);
290 struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
293 txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
299 struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
302 txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
308 struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
311 txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
317 struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
320 txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
327 struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
329 &txgpio->line_entries[irqd_to_hwirq(d)];
343 raw_spin_lock(&txgpio->lock);
346 set_bit(txline->line, txgpio->invert_mask);
348 clear_bit(txline->line, txgpio->invert_mask);
350 clear_bit(txline->line, txgpio->od_mask);
351 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line));
352 raw_spin_unlock(&txgpio->lock);
402 struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
406 irq = txgpio->msix_entries[child].vector;
431 struct thunderx_gpio *txgpio;
437 txgpio = devm_kzalloc(dev, sizeof(*txgpio), GFP_KERNEL);
438 if (!txgpio)
441 raw_spin_lock_init(&txgpio->lock);
442 chip = &txgpio->chip;
444 pci_set_drvdata(pdev, txgpio);
459 txgpio->register_base = tbl[0];
460 if (!txgpio->register_base) {
469 txgpio->base_msi = 48;
471 u64 c = readq(txgpio->register_base + GPIO_CONST);
474 txgpio->base_msi = (c >> 8) & 0xff;
477 txgpio->msix_entries = devm_kcalloc(dev,
480 if (!txgpio->msix_entries) {
485 txgpio->line_entries = devm_kcalloc(dev,
489 if (!txgpio->line_entries) {
495 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(i));
497 txgpio->msix_entries[i].entry = txgpio->base_msi + (2 * i);
498 txgpio->line_entries[i].line = i;
499 txgpio->line_entries[i].txgpio = txgpio;
505 txgpio->line_entries[i].fil_bits = bit_cfg ?
509 set_bit(i, txgpio->od_mask);
511 set_bit(i, txgpio->invert_mask);
516 err = pci_enable_msix_range(pdev, txgpio->msix_entries, ngpio, ngpio);
538 irq_get_irq_data(txgpio->msix_entries[0].vector)->domain;
544 err = devm_gpiochip_add_data(dev, chip, txgpio);
557 txgpio->msix_entries[i].vector,
574 struct thunderx_gpio *txgpio = pci_get_drvdata(pdev);
576 for (i = 0; i < txgpio->chip.ngpio; i++)
577 irq_domain_pop_irq(txgpio->chip.irq.domain,
578 txgpio->msix_entries[i].vector);
580 irq_domain_remove(txgpio->chip.irq.domain);