Lines Matching refs:sch
50 static unsigned int sch_gpio_offset(struct sch_gpio *sch, unsigned int gpio,
55 if (gpio >= sch->resume_base) {
56 gpio -= sch->resume_base;
63 static unsigned int sch_gpio_bit(struct sch_gpio *sch, unsigned int gpio)
65 if (gpio >= sch->resume_base)
66 gpio -= sch->resume_base;
70 static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned int gpio, unsigned int reg)
75 offset = sch_gpio_offset(sch, gpio, reg);
76 bit = sch_gpio_bit(sch, gpio);
78 reg_val = !!(inb(sch->iobase + offset) & BIT(bit));
83 static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned int gpio, unsigned int reg,
89 offset = sch_gpio_offset(sch, gpio, reg);
90 bit = sch_gpio_bit(sch, gpio);
92 reg_val = inb(sch->iobase + offset);
95 outb(reg_val | BIT(bit), sch->iobase + offset);
97 outb((reg_val & ~BIT(bit)), sch->iobase + offset);
102 struct sch_gpio *sch = gpiochip_get_data(gc);
105 spin_lock_irqsave(&sch->lock, flags);
106 sch_gpio_reg_set(sch, gpio_num, GIO, 1);
107 spin_unlock_irqrestore(&sch->lock, flags);
113 struct sch_gpio *sch = gpiochip_get_data(gc);
115 return sch_gpio_reg_get(sch, gpio_num, GLV);
120 struct sch_gpio *sch = gpiochip_get_data(gc);
123 spin_lock_irqsave(&sch->lock, flags);
124 sch_gpio_reg_set(sch, gpio_num, GLV, val);
125 spin_unlock_irqrestore(&sch->lock, flags);
131 struct sch_gpio *sch = gpiochip_get_data(gc);
134 spin_lock_irqsave(&sch->lock, flags);
135 sch_gpio_reg_set(sch, gpio_num, GIO, 0);
136 spin_unlock_irqrestore(&sch->lock, flags);
153 struct sch_gpio *sch = gpiochip_get_data(gc);
155 if (sch_gpio_reg_get(sch, gpio_num, GIO))
174 struct sch_gpio *sch = gpiochip_get_data(gc);
196 spin_lock_irqsave(&sch->lock, flags);
198 sch_gpio_reg_set(sch, gpio_num, GTPE, rising);
199 sch_gpio_reg_set(sch, gpio_num, GTNE, falling);
203 spin_unlock_irqrestore(&sch->lock, flags);
211 struct sch_gpio *sch = gpiochip_get_data(gc);
215 spin_lock_irqsave(&sch->lock, flags);
216 sch_gpio_reg_set(sch, gpio_num, GTS, 1);
217 spin_unlock_irqrestore(&sch->lock, flags);
222 struct sch_gpio *sch = gpiochip_get_data(gc);
225 spin_lock_irqsave(&sch->lock, flags);
226 sch_gpio_reg_set(sch, gpio_num, GGPE, val);
227 spin_unlock_irqrestore(&sch->lock, flags);
260 struct sch_gpio *sch = context;
261 struct gpio_chip *gc = &sch->chip;
268 spin_lock_irqsave(&sch->lock, flags);
270 core_status = inl(sch->iobase + CORE_BANK_OFFSET + GTS);
271 resume_status = inl(sch->iobase + RESUME_BANK_OFFSET + GTS);
273 spin_unlock_irqrestore(&sch->lock, flags);
275 pending = (resume_status << sch->resume_base) | core_status;
276 for_each_set_bit(offset, &pending, sch->chip.ngpio)
290 struct sch_gpio *sch = data;
292 acpi_disable_gpe(NULL, sch->gpe);
293 acpi_remove_gpe_handler(NULL, sch->gpe, sch->gpe_handler);
296 static int sch_gpio_install_gpe_handler(struct sch_gpio *sch)
298 struct device *dev = sch->chip.parent;
301 status = acpi_install_gpe_handler(NULL, sch->gpe, ACPI_GPE_LEVEL_TRIGGERED,
302 sch->gpe_handler, sch);
305 sch->gpe, acpi_format_exception(status));
309 status = acpi_enable_gpe(NULL, sch->gpe);
312 sch->gpe, acpi_format_exception(status));
313 acpi_remove_gpe_handler(NULL, sch->gpe, sch->gpe_handler);
317 return devm_add_action_or_reset(dev, sch_gpio_remove_gpe_handler, sch);
323 struct sch_gpio *sch;
327 sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL);
328 if (!sch)
339 spin_lock_init(&sch->lock);
340 sch->iobase = res->start;
341 sch->chip = sch_gpio_chip;
342 sch->chip.label = dev_name(&pdev->dev);
343 sch->chip.parent = &pdev->dev;
347 sch->resume_base = 10;
348 sch->chip.ngpio = 14;
355 sch_gpio_reg_set(sch, 8, GEN, 1);
356 sch_gpio_reg_set(sch, 9, GEN, 1);
361 sch_gpio_reg_set(sch, 13, GEN, 1);
365 sch->resume_base = 5;
366 sch->chip.ngpio = 14;
370 sch->resume_base = 21;
371 sch->chip.ngpio = 30;
375 sch->resume_base = 2;
376 sch->chip.ngpio = 8;
383 girq = &sch->chip.irq;
392 sch->gpe = GPE0E_GPIO;
393 sch->gpe_handler = sch_gpio_gpe_handler;
395 ret = sch_gpio_install_gpe_handler(sch);
399 return devm_gpiochip_add_data(&pdev->dev, &sch->chip, sch);