Lines Matching refs:pl061
51 struct pl061 {
65 struct pl061 *pl061 = gpiochip_get_data(gc);
67 if (readb(pl061->base + GPIODIR) & BIT(offset))
75 struct pl061 *pl061 = gpiochip_get_data(gc);
79 raw_spin_lock_irqsave(&pl061->lock, flags);
80 gpiodir = readb(pl061->base + GPIODIR);
82 writeb(gpiodir, pl061->base + GPIODIR);
83 raw_spin_unlock_irqrestore(&pl061->lock, flags);
91 struct pl061 *pl061 = gpiochip_get_data(gc);
95 raw_spin_lock_irqsave(&pl061->lock, flags);
96 writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
97 gpiodir = readb(pl061->base + GPIODIR);
99 writeb(gpiodir, pl061->base + GPIODIR);
102 * gpio value is set again, because pl061 doesn't allow to set value of
105 writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
106 raw_spin_unlock_irqrestore(&pl061->lock, flags);
113 struct pl061 *pl061 = gpiochip_get_data(gc);
115 return !!readb(pl061->base + (BIT(offset + 2)));
120 struct pl061 *pl061 = gpiochip_get_data(gc);
122 writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
128 struct pl061 *pl061 = gpiochip_get_data(gc);
148 raw_spin_lock_irqsave(&pl061->lock, flags);
150 gpioiev = readb(pl061->base + GPIOIEV);
151 gpiois = readb(pl061->base + GPIOIS);
152 gpioibe = readb(pl061->base + GPIOIBE);
204 writeb(gpiois, pl061->base + GPIOIS);
205 writeb(gpioibe, pl061->base + GPIOIBE);
206 writeb(gpioiev, pl061->base + GPIOIEV);
208 raw_spin_unlock_irqrestore(&pl061->lock, flags);
218 struct pl061 *pl061 = gpiochip_get_data(gc);
223 pending = readb(pl061->base + GPIOMIS);
236 struct pl061 *pl061 = gpiochip_get_data(gc);
240 raw_spin_lock(&pl061->lock);
241 gpioie = readb(pl061->base + GPIOIE) & ~mask;
242 writeb(gpioie, pl061->base + GPIOIE);
243 raw_spin_unlock(&pl061->lock);
251 struct pl061 *pl061 = gpiochip_get_data(gc);
257 raw_spin_lock(&pl061->lock);
258 gpioie = readb(pl061->base + GPIOIE) | mask;
259 writeb(gpioie, pl061->base + GPIOIE);
260 raw_spin_unlock(&pl061->lock);
274 struct pl061 *pl061 = gpiochip_get_data(gc);
277 raw_spin_lock(&pl061->lock);
278 writeb(mask, pl061->base + GPIOIC);
279 raw_spin_unlock(&pl061->lock);
285 struct pl061 *pl061 = gpiochip_get_data(gc);
287 return irq_set_irq_wake(pl061->parent_irq, state);
311 struct pl061 *pl061;
315 pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL);
316 if (pl061 == NULL)
319 pl061->base = devm_ioremap_resource(dev, &adev->res);
320 if (IS_ERR(pl061->base))
321 return PTR_ERR(pl061->base);
323 raw_spin_lock_init(&pl061->lock);
324 pl061->gc.request = gpiochip_generic_request;
325 pl061->gc.free = gpiochip_generic_free;
326 pl061->gc.base = -1;
327 pl061->gc.get_direction = pl061_get_direction;
328 pl061->gc.direction_input = pl061_direction_input;
329 pl061->gc.direction_output = pl061_direction_output;
330 pl061->gc.get = pl061_get_value;
331 pl061->gc.set = pl061_set_value;
332 pl061->gc.ngpio = PL061_GPIO_NR;
333 pl061->gc.label = dev_name(dev);
334 pl061->gc.parent = dev;
335 pl061->gc.owner = THIS_MODULE;
340 writeb(0, pl061->base + GPIOIE); /* disable irqs */
344 pl061->parent_irq = irq;
346 girq = &pl061->gc.irq;
358 ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061);
362 amba_set_drvdata(adev, pl061);
371 struct pl061 *pl061 = dev_get_drvdata(dev);
374 pl061->csave_regs.gpio_data = 0;
375 pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);
376 pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);
377 pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);
378 pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);
379 pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);
382 if (pl061->csave_regs.gpio_dir & (BIT(offset)))
383 pl061->csave_regs.gpio_data |=
384 pl061_get_value(&pl061->gc, offset) << offset;
392 struct pl061 *pl061 = dev_get_drvdata(dev);
396 if (pl061->csave_regs.gpio_dir & (BIT(offset)))
397 pl061_direction_output(&pl061->gc, offset,
398 pl061->csave_regs.gpio_data &
401 pl061_direction_input(&pl061->gc, offset);
404 writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);
405 writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);
406 writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);
407 writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);