Lines Matching refs:chip

106 	struct pch_gpio *chip =	gpiochip_get_data(gpio);
109 	spin_lock_irqsave(&chip->spinlock, flags);
110 	reg_val = ioread32(&chip->reg->po);
116 	iowrite32(reg_val, &chip->reg->po);
117 	spin_unlock_irqrestore(&chip->spinlock, flags);
122 	struct pch_gpio *chip =	gpiochip_get_data(gpio);
124 	return !!(ioread32(&chip->reg->pi) & BIT(nr));
130 	struct pch_gpio *chip =	gpiochip_get_data(gpio);
135 	spin_lock_irqsave(&chip->spinlock, flags);
137 	reg_val = ioread32(&chip->reg->po);
142 	iowrite32(reg_val, &chip->reg->po);
144 	pm = ioread32(&chip->reg->pm);
145 	pm &= BIT(gpio_pins[chip->ioh]) - 1;
147 	iowrite32(pm, &chip->reg->pm);
149 	spin_unlock_irqrestore(&chip->spinlock, flags);
156 	struct pch_gpio *chip =	gpiochip_get_data(gpio);
160 	spin_lock_irqsave(&chip->spinlock, flags);
161 	pm = ioread32(&chip->reg->pm);
162 	pm &= BIT(gpio_pins[chip->ioh]) - 1;
164 	iowrite32(pm, &chip->reg->pm);
165 	spin_unlock_irqrestore(&chip->spinlock, flags);
173 static void __maybe_unused pch_gpio_save_reg_conf(struct pch_gpio *chip)
175 	chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
176 	chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
177 	chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
178 	chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
179 	chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
180 	if (chip->ioh == INTEL_EG20T_PCH)
181 		chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
182 	if (chip->ioh == OKISEMI_ML7223n_IOH)
183 		chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel);
189 static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip)
191 	iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
192 	iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
194 	iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
196 	iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
197 	iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
198 	if (chip->ioh == INTEL_EG20T_PCH)
199 		iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
200 	if (chip->ioh == OKISEMI_ML7223n_IOH)
201 		iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel);
206 	struct pch_gpio *chip = gpiochip_get_data(gpio);
208 	return chip->irq_base + offset;
211 static void pch_gpio_setup(struct pch_gpio *chip)
213 	struct gpio_chip *gpio = &chip->gpio;
215 	gpio->label = dev_name(chip->dev);
216 	gpio->parent = chip->dev;
223 	gpio->ngpio = gpio_pins[chip->ioh];
231 	struct pch_gpio *chip = gc->private;
237 	ch = irq - chip->irq_base;
238 	if (irq < chip->irq_base + 8) {
239 		im_reg = &chip->reg->im0;
242 		im_reg = &chip->reg->im1;
245 	dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos);
267 	spin_lock_irqsave(&chip->spinlock, flags);
279 	spin_unlock_irqrestore(&chip->spinlock, flags);
286 	struct pch_gpio *chip = gc->private;
288 	iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imaskclr);
294 	struct pch_gpio *chip = gc->private;
296 	iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imask);
302 	struct pch_gpio *chip = gc->private;
304 	iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->iclr);
309 	struct pch_gpio *chip = dev_id;
310 	unsigned long reg_val = ioread32(&chip->reg->istatus);
313 	dev_vdbg(chip->dev, "irq=%d  status=0x%lx\n", irq, reg_val);
315 	reg_val &= BIT(gpio_pins[chip->ioh]) - 1;
317 	for_each_set_bit(i, &reg_val, gpio_pins[chip->ioh])
318 		generic_handle_irq(chip->irq_base + i);
323 static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
331 	gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start,
332 					 chip->base, handle_simple_irq);
336 	gc->private = chip;
339 	ct->chip.irq_ack = pch_irq_ack;
340 	ct->chip.irq_mask = pch_irq_mask;
341 	ct->chip.irq_unmask = pch_irq_unmask;
342 	ct->chip.irq_set_type = pch_irq_type;
344 	rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
356 	struct pch_gpio *chip;
359 	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
360 	if (chip == NULL)
363 	chip->dev = dev;
372 	chip->base = pcim_iomap_table(pdev)[1];
373 	chip->ioh = id->driver_data;
374 	chip->reg = chip->base;
375 	pci_set_drvdata(pdev, chip);
376 	spin_lock_init(&chip->spinlock);
377 	pch_gpio_setup(chip);
379 	ret = devm_gpiochip_add_data(dev, &chip->gpio, chip);
384 					gpio_pins[chip->ioh], NUMA_NO_NODE);
387 		chip->irq_base = -1;
390 	chip->irq_base = irq_base;
393 	iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->imask);
394 	iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->ien);
397 			       IRQF_SHARED, KBUILD_MODNAME, chip);
401 	return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
406 	struct pch_gpio *chip = dev_get_drvdata(dev);
409 	spin_lock_irqsave(&chip->spinlock, flags);
410 	pch_gpio_save_reg_conf(chip);
411 	spin_unlock_irqrestore(&chip->spinlock, flags);
418 	struct pch_gpio *chip = dev_get_drvdata(dev);
421 	spin_lock_irqsave(&chip->spinlock, flags);
422 	iowrite32(0x01, &chip->reg->reset);
423 	iowrite32(0x00, &chip->reg->reset);
424 	pch_gpio_restore_reg_conf(chip);
425 	spin_unlock_irqrestore(&chip->spinlock, flags);