Lines Matching refs:port
57 static inline int is_imx23_gpio(struct mxs_gpio_port *port)
59 return port->devid == IMX23_GPIO;
70 struct mxs_gpio_port *port = gc->private;
78 port->both_edges &= ~pin_mask;
81 val = readl(port->base + PINCTRL_DIN(port)) & pin_mask;
86 port->both_edges |= pin_mask;
105 pin_addr = port->base + PINCTRL_IRQLEV(port);
108 writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
111 writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
115 pin_addr = port->base + PINCTRL_IRQPOL(port);
121 writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
126 static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
133 pin_addr = port->base + PINCTRL_IRQPOL(port);
143 /* MXS has one interrupt *per* gpio port */
147 struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
151 irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
152 readl(port->base + PINCTRL_IRQEN(port));
156 if (port->both_edges & (1 << irqoffset))
157 mxs_flip_edge(port, irqoffset);
159 generic_handle_domain_irq(port->domain, irqoffset);
176 struct mxs_gpio_port *port = gc->private;
179 enable_irq_wake(port->irq);
181 disable_irq_wake(port->irq);
186 static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
192 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
193 port->base, handle_level_irq);
197 gc->private = port;
207 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
208 ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
209 ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;
219 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
220 ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
221 ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
224 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
233 struct mxs_gpio_port *port = gpiochip_get_data(gc);
235 return irq_find_mapping(port->domain, offset);
240 struct mxs_gpio_port *port = gpiochip_get_data(gc);
244 dir = readl(port->base + PINCTRL_DOE(port));
263 struct mxs_gpio_port *port;
267 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
268 if (!port)
271 port->id = of_alias_get_id(np, "gpio");
272 if (port->id < 0)
273 return port->id;
274 port->devid = (uintptr_t)of_device_get_match_data(&pdev->dev);
275 port->dev = &pdev->dev;
276 port->irq = platform_get_irq(pdev, 0);
277 if (port->irq < 0)
278 return port->irq;
291 port->base = base;
294 writel(0, port->base + PINCTRL_PIN2IRQ(port));
295 writel(0, port->base + PINCTRL_IRQEN(port));
298 writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
306 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
308 if (!port->domain) {
314 err = mxs_gpio_init_gc(port, irq_base);
319 irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
320 port);
322 err = bgpio_init(&port->gc, &pdev->dev, 4,
323 port->base + PINCTRL_DIN(port),
324 port->base + PINCTRL_DOUT(port) + MXS_SET,
325 port->base + PINCTRL_DOUT(port) + MXS_CLR,
326 port->base + PINCTRL_DOE(port), NULL, 0);
330 port->gc.to_irq = mxs_gpio_to_irq;
331 port->gc.get_direction = mxs_gpio_get_direction;
332 port->gc.base = port->id * 32;
334 err = gpiochip_add_data(&port->gc, port);
341 irq_domain_remove(port->domain);
343 iounmap(port->base);