Lines Matching refs:port
123 #define GPIO_DR (port->hwdata->dr_reg)
124 #define GPIO_GDIR (port->hwdata->gdir_reg)
125 #define GPIO_PSR (port->hwdata->psr_reg)
126 #define GPIO_ICR1 (port->hwdata->icr1_reg)
127 #define GPIO_ICR2 (port->hwdata->icr2_reg)
128 #define GPIO_IMR (port->hwdata->imr_reg)
129 #define GPIO_ISR (port->hwdata->isr_reg)
130 #define GPIO_EDGE_SEL (port->hwdata->edge_sel_reg)
132 #define GPIO_INT_LOW_LEV (port->hwdata->low_level)
133 #define GPIO_INT_HIGH_LEV (port->hwdata->high_level)
134 #define GPIO_INT_RISE_EDGE (port->hwdata->rise_edge)
135 #define GPIO_INT_FALL_EDGE (port->hwdata->fall_edge)
163 struct mxc_gpio_port *port = gc->private;
168 void __iomem *reg = port->base;
170 port->both_edges &= ~(1 << gpio_idx);
182 val = port->gc.get(&port->gc, gpio_idx);
190 port->both_edges |= 1 << gpio_idx;
203 raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags);
206 val = readl(port->base + GPIO_EDGE_SEL);
209 port->base + GPIO_EDGE_SEL);
212 port->base + GPIO_EDGE_SEL);
222 writel(1 << gpio_idx, port->base + GPIO_ISR);
223 port->pad_type[gpio_idx] = type;
225 raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags);
227 return port->gc.direction_input(&port->gc, gpio_idx);
230 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
232 void __iomem *reg = port->base;
237 raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags);
258 raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags);
262 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
267 if (port->both_edges & (1 << irqoffset))
268 mxc_flip_edge(port, irqoffset);
270 generic_handle_domain_irq(port->domain, irqoffset);
276 /* MX1 and MX3 has one interrupt *per* gpio port */
280 struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
283 if (port->is_pad_wakeup)
288 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
290 mxc_gpio_irq_handler(port, irq_stat);
299 struct mxc_gpio_port *port;
305 list_for_each_entry(port, &mxc_gpio_ports, node) {
306 irq_msk = readl(port->base + GPIO_IMR);
310 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
312 mxc_gpio_irq_handler(port, irq_stat);
329 struct mxc_gpio_port *port = gc->private;
334 if (port->irq_high && (gpio_idx >= 16))
335 ret = enable_irq_wake(port->irq_high);
337 ret = enable_irq_wake(port->irq);
338 port->wakeup_pads |= (1 << gpio_idx);
340 if (port->irq_high && (gpio_idx >= 16))
341 ret = disable_irq_wake(port->irq_high);
343 ret = disable_irq_wake(port->irq);
344 port->wakeup_pads &= ~(1 << gpio_idx);
350 static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
356 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
357 port->base, handle_level_irq);
360 gc->private = port;
372 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
381 struct mxc_gpio_port *port = gpiochip_get_data(gc);
383 return irq_find_mapping(port->domain, offset);
403 static void mxc_update_irq_chained_handler(struct mxc_gpio_port *port, bool enable)
406 irq_set_chained_handler_and_data(port->irq, port->mx_irq_handler, port);
408 irq_set_chained_handler_and_data(port->irq, NULL, NULL);
411 if (port->irq_high > 0) {
413 irq_set_chained_handler_and_data(port->irq_high,
414 port->mx_irq_handler,
415 port);
417 irq_set_chained_handler_and_data(port->irq_high, NULL, NULL);
424 struct mxc_gpio_port *port;
429 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
430 if (!port)
433 port->dev = &pdev->dev;
434 port->hwdata = device_get_match_data(&pdev->dev);
436 port->base = devm_platform_ioremap_resource(pdev, 0);
437 if (IS_ERR(port->base))
438 return PTR_ERR(port->base);
445 port->irq_high = platform_get_irq(pdev, 1);
446 if (port->irq_high < 0)
447 port->irq_high = 0;
450 port->irq = platform_get_irq(pdev, 0);
451 if (port->irq < 0)
452 return port->irq;
455 port->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);
456 if (IS_ERR(port->clk))
457 return PTR_ERR(port->clk);
460 port->power_off = true;
467 writel(0, port->base + GPIO_IMR);
468 writel(~0, port->base + GPIO_ISR);
473 * the handler is needed only once, but doing it for every port
476 port->irq_high = -1;
477 port->mx_irq_handler = mx2_gpio_irq_handler;
479 port->mx_irq_handler = mx3_gpio_irq_handler;
481 mxc_update_irq_chained_handler(port, true);
482 err = bgpio_init(&port->gc, &pdev->dev, 4,
483 port->base + GPIO_PSR,
484 port->base + GPIO_DR, NULL,
485 port->base + GPIO_GDIR, NULL,
490 port->gc.request = mxc_gpio_request;
491 port->gc.free = mxc_gpio_free;
492 port->gc.to_irq = mxc_gpio_to_irq;
493 port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
496 err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
506 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
508 if (!port->domain) {
513 irq_domain_set_pm_device(port->domain, &pdev->dev);
516 err = mxc_gpio_init_gc(port, irq_base);
520 list_add_tail(&port->node, &mxc_gpio_ports);
522 platform_set_drvdata(pdev, port);
528 irq_domain_remove(port->domain);
536 static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
538 if (!port->power_off)
541 port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
542 port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
543 port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
544 port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
545 port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
546 port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
549 static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
551 if (!port->power_off)
554 writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
555 writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
556 writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
557 writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
558 writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
559 writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
562 static bool mxc_gpio_generic_config(struct mxc_gpio_port *port,
565 struct device_node *np = port->dev->of_node;
570 return (gpiochip_generic_config(&port->gc, offset, conf) == 0);
575 static bool mxc_gpio_set_pad_wakeup(struct mxc_gpio_port *port, bool enable)
594 if ((port->wakeup_pads & (1 << i))) {
595 type = port->pad_type[i];
600 ret |= mxc_gpio_generic_config(port, i, config);
609 struct mxc_gpio_port *port = dev_get_drvdata(dev);
611 mxc_gpio_save_regs(port);
612 clk_disable_unprepare(port->clk);
613 mxc_update_irq_chained_handler(port, false);
620 struct mxc_gpio_port *port = dev_get_drvdata(dev);
623 mxc_update_irq_chained_handler(port, true);
624 ret = clk_prepare_enable(port->clk);
626 mxc_update_irq_chained_handler(port, false);
630 mxc_gpio_restore_regs(port);
638 struct mxc_gpio_port *port = platform_get_drvdata(pdev);
640 if (port->wakeup_pads > 0)
641 port->is_pad_wakeup = mxc_gpio_set_pad_wakeup(port, true);
649 struct mxc_gpio_port *port = platform_get_drvdata(pdev);
651 if (port->wakeup_pads > 0)
652 mxc_gpio_set_pad_wakeup(port, false);
653 port->is_pad_wakeup = false;
665 struct mxc_gpio_port *port;
669 list_for_each_entry(port, &mxc_gpio_ports, node) {
670 ret = clk_prepare_enable(port->clk);
673 mxc_gpio_save_regs(port);
674 clk_disable_unprepare(port->clk);
682 struct mxc_gpio_port *port;
686 list_for_each_entry(port, &mxc_gpio_ports, node) {
687 ret = clk_prepare_enable(port->clk);
692 mxc_gpio_restore_regs(port);
693 clk_disable_unprepare(port->clk);