Lines Matching refs:mvpwm
122 struct mvebu_pwm *mvpwm;
287 static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
289 return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF;
292 static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
294 return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF;
622 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
623 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
628 spin_lock_irqsave(&mvpwm->lock, flags);
630 if (mvpwm->gpiod) {
642 mvpwm->gpiod = desc;
645 spin_unlock_irqrestore(&mvpwm->lock, flags);
651 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
654 spin_lock_irqsave(&mvpwm->lock, flags);
655 gpiochip_free_own_desc(mvpwm->gpiod);
656 mvpwm->gpiod = NULL;
657 spin_unlock_irqrestore(&mvpwm->lock, flags);
665 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
666 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
671 spin_lock_irqsave(&mvpwm->lock, flags);
673 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u);
680 mvpwm->clk_rate);
682 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u);
688 state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate);
696 spin_unlock_irqrestore(&mvpwm->lock, flags);
704 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
705 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
713 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
728 val = (unsigned long long) mvpwm->clk_rate * state->period;
740 spin_lock_irqsave(&mvpwm->lock, flags);
742 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on);
743 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off);
749 spin_unlock_irqrestore(&mvpwm->lock, flags);
764 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
767 &mvpwm->blink_select);
768 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm),
769 &mvpwm->blink_on_duration);
770 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm),
771 &mvpwm->blink_off_duration);
776 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
779 mvpwm->blink_select);
780 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm),
781 mvpwm->blink_on_duration);
782 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm),
783 mvpwm->blink_off_duration);
791 struct mvebu_pwm *mvpwm;
816 mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
817 if (!mvpwm)
819 mvchip->mvpwm = mvpwm;
820 mvpwm->mvchip = mvchip;
821 mvpwm->offset = offset;
824 mvpwm->regs = mvchip->regs;
835 mvpwm->offset += PWM_BLINK_COUNTER_B_OFF;
845 mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base,
847 if (IS_ERR(mvpwm->regs))
848 return PTR_ERR(mvpwm->regs);
865 mvpwm->clk_rate = clk_get_rate(mvchip->clk);
866 if (!mvpwm->clk_rate) {
871 mvpwm->chip.dev = dev;
872 mvpwm->chip.ops = &mvebu_pwm_ops;
873 mvpwm->chip.npwm = mvchip->chip.ngpio;
875 spin_lock_init(&mvpwm->lock);
877 return devm_pwmchip_add(dev, &mvpwm->chip);