Lines Matching refs:mvchip
103 struct mvebu_gpio_chip *mvchip;
138 static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
143 switch (mvchip->soc_variant) {
147 *map = mvchip->regs;
148 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
152 *map = mvchip->percpu_regs;
161 mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
167 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
174 mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
179 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
184 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
189 switch (mvchip->soc_variant) {
192 *map = mvchip->regs;
193 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
197 *map = mvchip->regs;
202 *map = mvchip->percpu_regs;
211 mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
217 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
224 mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
229 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
234 mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
239 switch (mvchip->soc_variant) {
242 *map = mvchip->regs;
243 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
247 *map = mvchip->regs;
252 *map = mvchip->percpu_regs;
261 mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
267 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
274 mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
279 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
302 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
304 regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
310 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
313 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
318 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
320 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
324 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u);
333 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
335 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
341 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
352 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
361 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
375 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
383 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
386 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
396 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
398 return irq_create_mapping(mvchip->domain, pin);
407 struct mvebu_gpio_chip *mvchip = gc->private;
411 mvebu_gpio_write_edge_cause(mvchip, ~mask);
418 struct mvebu_gpio_chip *mvchip = gc->private;
424 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
431 struct mvebu_gpio_chip *mvchip = gc->private;
436 mvebu_gpio_write_edge_cause(mvchip, ~mask);
438 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
445 struct mvebu_gpio_chip *mvchip = gc->private;
451 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
458 struct mvebu_gpio_chip *mvchip = gc->private;
464 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
498 struct mvebu_gpio_chip *mvchip = gc->private;
504 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
523 regmap_update_bits(mvchip->regs,
524 GPIO_IN_POL_OFF + mvchip->offset,
529 regmap_update_bits(mvchip->regs,
530 GPIO_IN_POL_OFF + mvchip->offset,
536 regmap_read(mvchip->regs,
537 GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
538 regmap_read(mvchip->regs,
539 GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
549 regmap_update_bits(mvchip->regs,
550 GPIO_IN_POL_OFF + mvchip->offset,
560 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
565 if (mvchip == NULL)
570 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
571 level_mask = mvebu_gpio_read_level_mask(mvchip);
572 edge_cause = mvebu_gpio_read_edge_cause(mvchip);
573 edge_mask = mvebu_gpio_read_edge_mask(mvchip);
577 for (i = 0; i < mvchip->chip.ngpio; i++) {
580 irq = irq_find_mapping(mvchip->domain, i);
590 regmap_read(mvchip->regs,
591 GPIO_IN_POL_OFF + mvchip->offset,
594 regmap_write(mvchip->regs,
595 GPIO_IN_POL_OFF + mvchip->offset,
623 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
633 desc = gpiochip_request_own_desc(&mvchip->chip,
666 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
690 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
705 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
745 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
747 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
762 static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
764 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
766 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
774 static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
776 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
778 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
787 struct mvebu_gpio_chip *mvchip,
796 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
813 if (IS_ERR(mvchip->clk))
814 return PTR_ERR(mvchip->clk);
819 mvchip->mvpwm = mvpwm;
820 mvpwm->mvchip = mvchip;
823 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
824 mvpwm->regs = mvchip->regs;
826 switch (mvchip->offset) {
862 regmap_write(mvchip->regs,
863 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
865 mvpwm->clk_rate = clk_get_rate(mvchip->clk);
873 mvpwm->chip.npwm = mvchip->chip.ngpio;
885 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
890 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out);
891 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf);
892 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink);
893 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
894 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
895 cause = mvebu_gpio_read_edge_cause(mvchip);
896 edg_msk = mvebu_gpio_read_edge_mask(mvchip);
897 lvl_msk = mvebu_gpio_read_level_mask(mvchip);
961 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
964 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
965 &mvchip->out_reg);
966 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
967 &mvchip->io_conf_reg);
968 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
969 &mvchip->blink_en_reg);
970 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
971 &mvchip->in_pol_reg);
973 switch (mvchip->soc_variant) {
976 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
977 &mvchip->edge_mask_regs[0]);
978 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
979 &mvchip->level_mask_regs[0]);
983 regmap_read(mvchip->regs,
985 &mvchip->edge_mask_regs[i]);
986 regmap_read(mvchip->regs,
988 &mvchip->level_mask_regs[i]);
993 regmap_read(mvchip->regs,
995 &mvchip->edge_mask_regs[i]);
996 regmap_read(mvchip->regs,
998 &mvchip->level_mask_regs[i]);
1006 mvebu_pwm_suspend(mvchip);
1013 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
1016 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
1017 mvchip->out_reg);
1018 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
1019 mvchip->io_conf_reg);
1020 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
1021 mvchip->blink_en_reg);
1022 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
1023 mvchip->in_pol_reg);
1025 switch (mvchip->soc_variant) {
1028 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
1029 mvchip->edge_mask_regs[0]);
1030 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
1031 mvchip->level_mask_regs[0]);
1035 regmap_write(mvchip->regs,
1037 mvchip->edge_mask_regs[i]);
1038 regmap_write(mvchip->regs,
1040 mvchip->level_mask_regs[i]);
1045 regmap_write(mvchip->regs,
1047 mvchip->edge_mask_regs[i]);
1048 regmap_write(mvchip->regs,
1050 mvchip->level_mask_regs[i]);
1058 mvebu_pwm_resume(mvchip);
1064 struct mvebu_gpio_chip *mvchip)
1072 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
1074 if (IS_ERR(mvchip->regs))
1075 return PTR_ERR(mvchip->regs);
1081 mvchip->offset = 0;
1087 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
1092 mvchip->percpu_regs =
1095 if (IS_ERR(mvchip->percpu_regs))
1096 return PTR_ERR(mvchip->percpu_regs);
1103 struct mvebu_gpio_chip *mvchip)
1105 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
1106 if (IS_ERR(mvchip->regs))
1107 return PTR_ERR(mvchip->regs);
1109 if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset))
1124 struct mvebu_gpio_chip *mvchip;
1148 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
1150 if (!mvchip)
1153 platform_set_drvdata(pdev, mvchip);
1166 mvchip->clk = devm_clk_get(&pdev->dev, NULL);
1168 if (!IS_ERR(mvchip->clk))
1169 clk_prepare_enable(mvchip->clk);
1171 mvchip->soc_variant = soc_variant;
1172 mvchip->chip.label = dev_name(&pdev->dev);
1173 mvchip->chip.parent = &pdev->dev;
1174 mvchip->chip.request = gpiochip_generic_request;
1175 mvchip->chip.free = gpiochip_generic_free;
1176 mvchip->chip.get_direction = mvebu_gpio_get_direction;
1177 mvchip->chip.direction_input = mvebu_gpio_direction_input;
1178 mvchip->chip.get = mvebu_gpio_get;
1179 mvchip->chip.direction_output = mvebu_gpio_direction_output;
1180 mvchip->chip.set = mvebu_gpio_set;
1182 mvchip->chip.to_irq = mvebu_gpio_to_irq;
1183 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
1184 mvchip->chip.ngpio = ngpios;
1185 mvchip->chip.can_sleep = false;
1186 mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
1189 err = mvebu_gpio_probe_syscon(pdev, mvchip);
1191 err = mvebu_gpio_probe_raw(pdev, mvchip);
1202 regmap_write(mvchip->regs,
1203 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0);
1204 regmap_write(mvchip->regs,
1205 GPIO_EDGE_MASK_OFF + mvchip->offset, 0);
1206 regmap_write(mvchip->regs,
1207 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0);
1210 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1212 regmap_write(mvchip->regs,
1214 regmap_write(mvchip->regs,
1219 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1220 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
1221 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
1223 regmap_write(mvchip->percpu_regs,
1225 regmap_write(mvchip->percpu_regs,
1227 regmap_write(mvchip->percpu_regs,
1235 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
1239 err = mvebu_pwm_probe(pdev, mvchip, id);
1248 mvchip->domain =
1250 if (!mvchip->domain) {
1252 mvchip->chip.label);
1257 mvchip->domain);
1262 mvchip->domain, ngpios, 2, np->name, handle_level_irq,
1266 mvchip->chip.label);
1274 gc = irq_get_domain_generic_chip(mvchip->domain, 0);
1275 gc->private = mvchip;
1281 ct->chip.name = mvchip->chip.label;
1290 ct->chip.name = mvchip->chip.label;
1303 mvchip);