Lines Matching refs:cause
27 * the normal cause/edge mask/level mask registers when the global
28 * interrupts are used, but adds per-CPU cause/edge mask/level mask
82 * The Armada XP has per-CPU registers for interrupt cause, interrupt
474 * Level IRQ handlers: DATA_IN is used directly as cause register.
484 * cause register.
486 * EDGE cause mask
488 * -----| |----- ---- to main cause reg
562 u32 cause, type, data_in, level_mask, edge_cause, edge_mask;
575 cause = (data_in & level_mask) | (edge_cause & edge_mask);
582 if (!(cause & BIT(i)))
886 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
895 cause = mvebu_gpio_read_edge_cause(mvchip);
926 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");