Lines Matching defs:set
23 * . register the device with -be`. .with a pair of set/clear-bit registers ,
343 gc->set(gc, gpio, val);
408 gc->set(gc, gpio, val);
415 gc->set(gc, gpio, val);
473 * - set/clear pair (named "set" and "clr").
474 * - single output register resource and single input resource ("set" and
478 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
479 * in the set register and clears it by setting a bit in the clear register.
492 void __iomem *set,
501 if (set && clr) {
502 gc->reg_set = set;
504 gc->set = bgpio_set_with_clear;
506 } else if (set && !clr) {
507 gc->reg_set = set;
508 gc->set = bgpio_set_set;
511 gc->set = bgpio_set_none;
514 gc->set = bgpio_set;
526 * their value in the set register when used as output. It is
576 * @gc: the GPIO chip to set up
582 * @set: MMIO address for the register to SET the value of the GPIO lines, it is
590 * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed
594 * @dirin: MMIO address for the register to set this line as INPUT. It is assumed
602 unsigned long sz, void __iomem *dat, void __iomem *set,
628 ret = bgpio_setup_io(gc, dat, set, clr, flags);
641 if (gc->set == bgpio_set_set &&
736 void __iomem *set;
765 set = bgpio_map(pdev, "set", sz);
766 if (IS_ERR(set))
767 return PTR_ERR(set);
785 err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);