Lines Matching refs:chip
95 struct ioh_gpio *chip = gpiochip_get_data(gpio);
98 spin_lock_irqsave(&chip->spinlock, flags);
99 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
105 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
106 spin_unlock_irqrestore(&chip->spinlock, flags);
111 struct ioh_gpio *chip = gpiochip_get_data(gpio);
113 return !!(ioread32(&chip->reg->regs[chip->ch].pi) & BIT(nr));
119 struct ioh_gpio *chip = gpiochip_get_data(gpio);
124 spin_lock_irqsave(&chip->spinlock, flags);
125 pm = ioread32(&chip->reg->regs[chip->ch].pm);
126 pm &= BIT(num_ports[chip->ch]) - 1;
128 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
130 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
135 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
137 spin_unlock_irqrestore(&chip->spinlock, flags);
144 struct ioh_gpio *chip = gpiochip_get_data(gpio);
148 spin_lock_irqsave(&chip->spinlock, flags);
149 pm = ioread32(&chip->reg->regs[chip->ch].pm);
150 pm &= BIT(num_ports[chip->ch]) - 1;
152 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
153 spin_unlock_irqrestore(&chip->spinlock, flags);
161 static void __maybe_unused ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
165 for (i = 0; i < 8; i ++, chip++) {
166 chip->ioh_gpio_reg.po_reg =
167 ioread32(&chip->reg->regs[chip->ch].po);
168 chip->ioh_gpio_reg.pm_reg =
169 ioread32(&chip->reg->regs[chip->ch].pm);
170 chip->ioh_gpio_reg.ien_reg =
171 ioread32(&chip->reg->regs[chip->ch].ien);
172 chip->ioh_gpio_reg.imask_reg =
173 ioread32(&chip->reg->regs[chip->ch].imask);
174 chip->ioh_gpio_reg.im0_reg =
175 ioread32(&chip->reg->regs[chip->ch].im_0);
176 chip->ioh_gpio_reg.im1_reg =
177 ioread32(&chip->reg->regs[chip->ch].im_1);
179 chip->ioh_gpio_reg.use_sel_reg =
180 ioread32(&chip->reg->ioh_sel_reg[i]);
187 static void __maybe_unused ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
191 for (i = 0; i < 8; i ++, chip++) {
192 iowrite32(chip->ioh_gpio_reg.po_reg,
193 &chip->reg->regs[chip->ch].po);
194 iowrite32(chip->ioh_gpio_reg.pm_reg,
195 &chip->reg->regs[chip->ch].pm);
196 iowrite32(chip->ioh_gpio_reg.ien_reg,
197 &chip->reg->regs[chip->ch].ien);
198 iowrite32(chip->ioh_gpio_reg.imask_reg,
199 &chip->reg->regs[chip->ch].imask);
200 iowrite32(chip->ioh_gpio_reg.im0_reg,
201 &chip->reg->regs[chip->ch].im_0);
202 iowrite32(chip->ioh_gpio_reg.im1_reg,
203 &chip->reg->regs[chip->ch].im_1);
205 iowrite32(chip->ioh_gpio_reg.use_sel_reg,
206 &chip->reg->ioh_sel_reg[i]);
212 struct ioh_gpio *chip = gpiochip_get_data(gpio);
213 return chip->irq_base + offset;
216 static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
218 struct gpio_chip *gpio = &chip->gpio;
220 gpio->label = dev_name(chip->dev);
244 struct ioh_gpio *chip = gc->private;
246 ch = irq - chip->irq_base;
247 if (irq <= chip->irq_base + 7) {
248 im_reg = &chip->reg->regs[chip->ch].im_0;
251 im_reg = &chip->reg->regs[chip->ch].im_1;
254 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
257 spin_lock_irqsave(&chip->spinlock, flags);
278 dev_warn(chip->dev, "%s: unknown type(%dd)",
288 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
291 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
294 ien = ioread32(&chip->reg->regs[chip->ch].ien);
295 iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
297 spin_unlock_irqrestore(&chip->spinlock, flags);
305 struct ioh_gpio *chip = gc->private;
307 iowrite32(BIT(d->irq - chip->irq_base),
308 &chip->reg->regs[chip->ch].imaskclr);
314 struct ioh_gpio *chip = gc->private;
316 iowrite32(BIT(d->irq - chip->irq_base),
317 &chip->reg->regs[chip->ch].imask);
323 struct ioh_gpio *chip = gc->private;
327 spin_lock_irqsave(&chip->spinlock, flags);
328 ien = ioread32(&chip->reg->regs[chip->ch].ien);
329 ien &= ~BIT(d->irq - chip->irq_base);
330 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
331 spin_unlock_irqrestore(&chip->spinlock, flags);
337 struct ioh_gpio *chip = gc->private;
341 spin_lock_irqsave(&chip->spinlock, flags);
342 ien = ioread32(&chip->reg->regs[chip->ch].ien);
343 ien |= BIT(d->irq - chip->irq_base);
344 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
345 spin_unlock_irqrestore(&chip->spinlock, flags);
350 struct ioh_gpio *chip = dev_id;
355 for (i = 0; i < 8; i++, chip++) {
356 reg_val = ioread32(&chip->reg->regs[i].istatus);
359 dev_dbg(chip->dev,
363 &chip->reg->regs[chip->ch].iclr);
364 generic_handle_irq(chip->irq_base + j);
372 static int ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
380 gc = devm_irq_alloc_generic_chip(chip->dev, "ioh_gpio", 1, irq_start,
381 chip->base, handle_simple_irq);
385 gc->private = chip;
388 ct->chip.irq_mask = ioh_irq_mask;
389 ct->chip.irq_unmask = ioh_irq_unmask;
390 ct->chip.irq_set_type = ioh_irq_type;
391 ct->chip.irq_disable = ioh_irq_disable;
392 ct->chip.irq_enable = ioh_irq_enable;
394 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
407 struct ioh_gpio *chip;
430 chip_save = devm_kcalloc(dev, 8, sizeof(*chip), GFP_KERNEL);
435 chip = chip_save;
436 for (i = 0; i < 8; i++, chip++) {
437 chip->dev = dev;
438 chip->base = base;
439 chip->reg = chip->base;
440 chip->ch = i;
441 spin_lock_init(&chip->spinlock);
442 ioh_gpio_setup(chip, num_ports[i]);
443 ret = devm_gpiochip_add_data(dev, &chip->gpio, chip);
450 chip = chip_save;
451 for (j = 0; j < 8; j++, chip++) {
459 chip->irq_base = irq_base;
461 ret = ioh_gpio_alloc_generic_chip(chip,
467 chip = chip_save;
469 IRQF_SHARED, KBUILD_MODNAME, chip);
475 pci_set_drvdata(pdev, chip);
482 struct ioh_gpio *chip = dev_get_drvdata(dev);
485 spin_lock_irqsave(&chip->spinlock, flags);
486 ioh_gpio_save_reg_conf(chip);
487 spin_unlock_irqrestore(&chip->spinlock, flags);
494 struct ioh_gpio *chip = dev_get_drvdata(dev);
497 spin_lock_irqsave(&chip->spinlock, flags);
498 iowrite32(0x01, &chip->reg->srst);
499 iowrite32(0x00, &chip->reg->srst);
500 ioh_gpio_restore_reg_conf(chip);
501 spin_unlock_irqrestore(&chip->spinlock, flags);