Lines Matching defs:desc
91 struct ichx_desc *desc; /* Pointer to chipset-specific description */
110 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
113 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
120 ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
122 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
125 tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
142 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
145 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
179 if (nr < 32 && ichx_priv.desc->have_blink)
235 if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f))
267 chip->request = ichx_priv.desc->request ?
268 ichx_priv.desc->request : ichx_gpio_request;
269 chip->get = ichx_priv.desc->get ?
270 ichx_priv.desc->get : ichx_gpio_get;
277 chip->ngpio = ichx_priv.desc->ngpio;
374 for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
378 res_base->start + ichx_priv.desc->regs[0][i],
379 ichx_priv.desc->reglen[i], name))
397 ichx_priv.desc = &i3100_desc;
400 ichx_priv.desc = &intel5_desc;
403 ichx_priv.desc = &ich6_desc;
406 ichx_priv.desc = &ich7_desc;
409 ichx_priv.desc = &ich9_desc;
412 ichx_priv.desc = &ich10_corp_desc;
415 ichx_priv.desc = &ich10_cons_desc;
418 ichx_priv.desc = &avoton_desc;
441 if (!ichx_priv.desc->uses_gpe0)