Lines Matching defs:hlwd
61 struct hlwd_gpio *hlwd =
69 raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
70 pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG);
71 pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
74 emulated_pending = hlwd->edge_emulation & pending;
79 level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
85 hlwd->regs + HW_GPIOB_INTLVL);
88 iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG);
91 rising &= hlwd->rising_edge;
92 falling &= hlwd->falling_edge;
97 raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
102 generic_handle_domain_irq(hlwd->gpioc.irq.domain, hwirq);
109 struct hlwd_gpio *hlwd =
112 iowrite32be(BIT(data->hwirq), hlwd->regs + HW_GPIOB_INTFLAG);
117 struct hlwd_gpio *hlwd =
122 raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
123 mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
125 iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
126 raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
127 gpiochip_disable_irq(&hlwd->gpioc, irqd_to_hwirq(data));
132 struct hlwd_gpio *hlwd =
137 gpiochip_enable_irq(&hlwd->gpioc, irqd_to_hwirq(data));
138 raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
139 mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
141 iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
142 raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
151 static void hlwd_gpio_irq_setup_emulation(struct hlwd_gpio *hlwd, int hwirq,
157 level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
158 state = ioread32be(hlwd->regs + HW_GPIOB_IN) & BIT(hwirq);
161 iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
163 hlwd->edge_emulation |= BIT(hwirq);
164 hlwd->rising_edge &= ~BIT(hwirq);
165 hlwd->falling_edge &= ~BIT(hwirq);
167 hlwd->rising_edge |= BIT(hwirq);
169 hlwd->falling_edge |= BIT(hwirq);
174 struct hlwd_gpio *hlwd =
179 raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
181 hlwd->edge_emulation &= ~BIT(data->hwirq);
185 level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
187 iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
190 level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
192 iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
197 hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type);
200 raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
204 raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
210 struct hlwd_gpio *hlwd =
213 seq_printf(p, dev_name(hlwd->dev));
228 struct hlwd_gpio *hlwd;
232 hlwd = devm_kzalloc(&pdev->dev, sizeof(*hlwd), GFP_KERNEL);
233 if (!hlwd)
236 hlwd->regs = devm_platform_ioremap_resource(pdev, 0);
237 if (IS_ERR(hlwd->regs))
238 return PTR_ERR(hlwd->regs);
240 hlwd->dev = &pdev->dev;
251 iowrite32be(0xffffffff, hlwd->regs + HW_GPIO_OWNER);
253 res = bgpio_init(&hlwd->gpioc, &pdev->dev, 4,
254 hlwd->regs + HW_GPIOB_IN, hlwd->regs + HW_GPIOB_OUT,
255 NULL, hlwd->regs + HW_GPIOB_DIR, NULL,
265 hlwd->gpioc.ngpio = ngpios;
268 iowrite32be(0, hlwd->regs + HW_GPIOB_INTMASK);
269 iowrite32be(0xffffffff, hlwd->regs + HW_GPIOB_INTFLAG);
278 hlwd->irq = platform_get_irq(pdev, 0);
279 if (hlwd->irq < 0) {
281 hlwd->irq);
282 return hlwd->irq;
285 girq = &hlwd->gpioc.irq;
294 girq->parents[0] = hlwd->irq;
299 return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc, hlwd);
310 .name = "gpio-hlwd",