Lines Matching refs:gpio
10 #include <linux/gpio/driver.h>
47 #define DWAPB_DRIVER_NAME "gpio-dwapb"
105 struct dwapb_gpio *gpio;
112 (container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
142 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
144 if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2)
150 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
152 struct gpio_chip *gc = &gpio->ports[0].gc;
153 void __iomem *reg_base = gpio->regs;
155 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
158 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
161 struct gpio_chip *gc = &gpio->ports[0].gc;
162 void __iomem *reg_base = gpio->regs;
164 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
167 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
172 for (i = 0; i < gpio->nr_ports; i++) {
173 port = &gpio->ports[i];
181 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
183 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
192 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
200 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
203 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
205 struct gpio_chip *gc = &gpio->ports[0].gc;
209 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
217 dwapb_toggle_trigger(gpio, hwirq);
225 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
229 dwapb_do_irq(gpio);
241 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
246 dwapb_write(gpio, GPIO_PORTA_EOI, val);
253 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
259 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
260 dwapb_write(gpio, GPIO_INTMASK, val);
269 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
277 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
278 dwapb_write(gpio, GPIO_INTMASK, val);
285 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
291 val = dwapb_read(gpio, GPIO_INTEN) | BIT(hwirq);
292 dwapb_write(gpio, GPIO_INTEN, val);
293 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
294 dwapb_write(gpio, GPIO_INTMASK, val);
301 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
307 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
308 dwapb_write(gpio, GPIO_INTMASK, val);
309 val = dwapb_read(gpio, GPIO_INTEN) & ~BIT(hwirq);
310 dwapb_write(gpio, GPIO_INTEN, val);
317 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
322 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
323 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
328 dwapb_toggle_trigger(gpio, bit);
353 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
355 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
365 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
366 struct dwapb_context *ctx = gpio->ports[0].ctx;
397 struct dwapb_gpio *gpio = port->gpio;
403 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
408 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
443 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
452 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);
457 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);
473 if (has_acpi_companion(gpio->dev)) {
478 err = devm_request_irq(gpio->dev, pp->irq[0],
480 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
482 dev_err(gpio->dev, "error requesting IRQ\n");
488 girq->parent_handler_data = gpio;
497 devm_kfree(gpio->dev, pirq);
500 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
508 port = &gpio->ports[offs];
509 port->gpio = gpio;
513 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
518 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;
519 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
520 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
523 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
526 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
541 dwapb_configure_irqs(gpio, port, pp);
543 err = devm_gpiochip_add_data(gpio->dev, &port->gc, port);
545 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
615 fwnode_property_read_u32(fwnode, "gpio-base", &pp->gpio_base);
630 struct dwapb_gpio *gpio = data;
632 reset_control_assert(gpio->rst);
635 static int dwapb_get_reset(struct dwapb_gpio *gpio)
639 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);
640 if (IS_ERR(gpio->rst))
641 return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst),
644 err = reset_control_deassert(gpio->rst);
646 dev_err(gpio->dev, "Cannot deassert reset lane\n");
650 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);
655 struct dwapb_gpio *gpio = data;
657 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
660 static int dwapb_get_clks(struct dwapb_gpio *gpio)
665 gpio->clks[0].id = "bus";
666 gpio->clks[1].id = "db";
667 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
668 gpio->clks);
670 return dev_err_probe(gpio->dev, err,
673 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
675 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");
679 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);
683 { .compatible = "snps,dw-apb-gpio", .data = (void *)GPIO_REG_OFFSET_V1},
684 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
700 struct dwapb_gpio *gpio;
709 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
710 if (!gpio)
713 gpio->dev = &pdev->dev;
714 gpio->nr_ports = pdata->nports;
716 err = dwapb_get_reset(gpio);
720 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
721 sizeof(*gpio->ports), GFP_KERNEL);
722 if (!gpio->ports)
725 gpio->regs = devm_platform_ioremap_resource(pdev, 0);
726 if (IS_ERR(gpio->regs))
727 return PTR_ERR(gpio->regs);
729 err = dwapb_get_clks(gpio);
733 gpio->flags = (uintptr_t)device_get_match_data(dev);
735 for (i = 0; i < gpio->nr_ports; i++) {
736 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
741 platform_set_drvdata(pdev, gpio);
749 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
750 struct gpio_chip *gc = &gpio->ports[0].gc;
755 for (i = 0; i < gpio->nr_ports; i++) {
757 unsigned int idx = gpio->ports[i].idx;
758 struct dwapb_context *ctx = gpio->ports[i].ctx;
761 ctx->dir = dwapb_read(gpio, offset);
764 ctx->data = dwapb_read(gpio, offset);
767 ctx->ext = dwapb_read(gpio, offset);
771 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
772 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
773 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
774 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
775 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
778 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
783 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
790 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
791 struct gpio_chip *gc = &gpio->ports[0].gc;
795 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
797 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
802 for (i = 0; i < gpio->nr_ports; i++) {
804 unsigned int idx = gpio->ports[i].idx;
805 struct dwapb_context *ctx = gpio->ports[i].ctx;
808 dwapb_write(gpio, offset, ctx->data);
811 dwapb_write(gpio, offset, ctx->dir);
814 dwapb_write(gpio, offset, ctx->ext);
818 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
819 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
820 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
821 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
822 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
825 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);