Lines Matching defs:bank
94 int bank = offset / 32;
97 g = d->regs[bank];
134 int bank = offset / 32;
136 g = d->regs[bank];
149 int bank = offset / 32;
151 g = d->regs[bank];
193 int bank, i, ret = 0;
260 for (bank = 0; bank < nbank; bank++)
261 chips->regs[bank] = gpio_base + offset_array[bank];
341 /* we only care about one bank */
478 unsigned gpio, bank;
535 * banked IRQs. Having GPIOs in the first GPIO bank use direct
548 /* pass "bank 0" GPIO IRQs to AINTC */
579 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
584 g = chips->regs[bank / 2];
589 * Each chip handles 32 gpios, and each irq bank consists of 16
590 * gpio irqs. Pass the irq bank's corresponding controller to
603 irqdata->bank_num = bank;
606 irq_set_chained_handler_and_data(chips->irqs[bank],
609 binten |= BIT(bank);
614 * BINTEN -- per-bank interrupt enable. genirq would also let these
627 u32 bank;
633 for (bank = 0; bank < nbank; bank++) {
634 g = chips->regs[bank];
635 context = &chips->context[bank];
651 u32 bank;
659 for (bank = 0; bank < nbank; bank++) {
660 g = chips->regs[bank];
661 context = &chips->context[bank];