Lines Matching refs:cg
114 static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg, int gpio)
119 if (cg->set_irq_mask)
120 regmap_update_bits(cg->regmap, mirqs0, mask, mask);
122 regmap_update_bits(cg->regmap, mirqs0, mask, 0);
125 static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
129 regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
134 struct crystalcove_gpio *cg = gpiochip_get_data(chip);
140 return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);
145 struct crystalcove_gpio *cg = gpiochip_get_data(chip);
151 return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value);
156 struct crystalcove_gpio *cg = gpiochip_get_data(chip);
163 ret = regmap_read(cg->regmap, reg, &val);
172 struct crystalcove_gpio *cg = gpiochip_get_data(chip);
179 regmap_update_bits(cg->regmap, reg, 1, 1);
181 regmap_update_bits(cg->regmap, reg, 1, 0);
186 struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
194 cg->intcnt_value = CTLI_INTCNT_DIS;
197 cg->intcnt_value = CTLI_INTCNT_BE;
200 cg->intcnt_value = CTLI_INTCNT_PE;
203 cg->intcnt_value = CTLI_INTCNT_NE;
209 cg->update |= UPDATE_IRQ_TYPE;
216 struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
218 mutex_lock(&cg->buslock);
223 struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
226 if (cg->update & UPDATE_IRQ_TYPE)
227 crystalcove_update_irq_ctrl(cg, hwirq);
228 if (cg->update & UPDATE_IRQ_MASK)
229 crystalcove_update_irq_mask(cg, hwirq);
230 cg->update = 0;
232 mutex_unlock(&cg->buslock);
238 struct crystalcove_gpio *cg = gpiochip_get_data(gc);
246 cg->set_irq_mask = false;
247 cg->update |= UPDATE_IRQ_MASK;
253 struct crystalcove_gpio *cg = gpiochip_get_data(gc);
259 cg->set_irq_mask = true;
260 cg->update |= UPDATE_IRQ_MASK;
278 struct crystalcove_gpio *cg = data;
284 if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||
285 regmap_read(cg->regmap, GPIO1IRQ, &p1))
288 regmap_write(cg->regmap, GPIO0IRQ, p0);
289 regmap_write(cg->regmap, GPIO1IRQ, p1);
294 virq = irq_find_mapping(cg->chip.irq.domain, gpio);
303 struct crystalcove_gpio *cg = gpiochip_get_data(chip);
308 regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
309 regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
310 regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
312 regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
314 regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
333 struct crystalcove_gpio *cg;
342 cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
343 if (!cg)
346 mutex_init(&cg->buslock);
347 cg->chip.label = KBUILD_MODNAME;
348 cg->chip.direction_input = crystalcove_gpio_dir_in;
349 cg->chip.direction_output = crystalcove_gpio_dir_out;
350 cg->chip.get = crystalcove_gpio_get;
351 cg->chip.set = crystalcove_gpio_set;
352 cg->chip.base = -1;
353 cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;
354 cg->chip.can_sleep = true;
355 cg->chip.parent = dev;
356 cg->chip.dbg_show = crystalcove_gpio_dbg_show;
357 cg->regmap = pmic->regmap;
359 girq = &cg->chip.irq;
371 IRQF_ONESHOT, KBUILD_MODNAME, cg);
377 retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg);
382 irq_domain_update_bus_token(cg->chip.irq.domain, DOMAIN_BUS_WIRED);