Lines Matching refs:cgpio
41 struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
46 iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) & ~BIT(offset),
47 cgpio->regs + CDNS_GPIO_BYPASS_MODE);
55 struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
60 iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) |
61 (BIT(offset) & cgpio->bypass_orig),
62 cgpio->regs + CDNS_GPIO_BYPASS_MODE);
70 struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
72 iowrite32(BIT(d->hwirq), cgpio->regs + CDNS_GPIO_IRQ_DIS);
79 struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
82 iowrite32(BIT(d->hwirq), cgpio->regs + CDNS_GPIO_IRQ_EN);
88 struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
97 int_value = ioread32(cgpio->regs + CDNS_GPIO_IRQ_VALUE) & ~mask;
98 int_type = ioread32(cgpio->regs + CDNS_GPIO_IRQ_TYPE) & ~mask;
116 iowrite32(int_value, cgpio->regs + CDNS_GPIO_IRQ_VALUE);
117 iowrite32(int_type, cgpio->regs + CDNS_GPIO_IRQ_TYPE);
127 struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
134 status = ioread32(cgpio->regs + CDNS_GPIO_IRQ_STATUS) &
135 ~ioread32(cgpio->regs + CDNS_GPIO_IRQ_MASK);
154 struct cdns_gpio_chip *cgpio;
159 cgpio = devm_kzalloc(&pdev->dev, sizeof(*cgpio), GFP_KERNEL);
160 if (!cgpio)
163 cgpio->regs = devm_platform_ioremap_resource(pdev, 0);
164 if (IS_ERR(cgpio->regs))
165 return PTR_ERR(cgpio->regs);
181 dir_prev = ioread32(cgpio->regs + CDNS_GPIO_DIRECTION_MODE);
183 cgpio->regs + CDNS_GPIO_DIRECTION_MODE);
185 ret = bgpio_init(&cgpio->gc, &pdev->dev, 4,
186 cgpio->regs + CDNS_GPIO_INPUT_VALUE,
187 cgpio->regs + CDNS_GPIO_OUTPUT_VALUE,
190 cgpio->regs + CDNS_GPIO_DIRECTION_MODE,
198 cgpio->gc.label = dev_name(&pdev->dev);
199 cgpio->gc.ngpio = num_gpios;
200 cgpio->gc.parent = &pdev->dev;
201 cgpio->gc.base = -1;
202 cgpio->gc.owner = THIS_MODULE;
203 cgpio->gc.request = cdns_gpio_request;
204 cgpio->gc.free = cdns_gpio_free;
206 cgpio->pclk = devm_clk_get(&pdev->dev, NULL);
207 if (IS_ERR(cgpio->pclk)) {
208 ret = PTR_ERR(cgpio->pclk);
214 ret = clk_prepare_enable(cgpio->pclk);
228 girq = &cgpio->gc.irq;
244 ret = devm_gpiochip_add_data(&pdev->dev, &cgpio->gc, cgpio);
250 cgpio->bypass_orig = ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE);
256 cgpio->regs + CDNS_GPIO_OUTPUT_EN);
257 iowrite32(0, cgpio->regs + CDNS_GPIO_BYPASS_MODE);
259 platform_set_drvdata(pdev, cgpio);
263 clk_disable_unprepare(cgpio->pclk);
266 iowrite32(dir_prev, cgpio->regs + CDNS_GPIO_DIRECTION_MODE);
273 struct cdns_gpio_chip *cgpio = platform_get_drvdata(pdev);
275 iowrite32(cgpio->bypass_orig, cgpio->regs + CDNS_GPIO_BYPASS_MODE);
276 clk_disable_unprepare(cgpio->pclk);