Lines Matching refs:ctrl
44 static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg)
46 return readl(ctrl->base + reg);
49 static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl,
52 writel(val, ctrl->base + reg);
56 struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits)
60 old_val = ath79_gpio_read(ctrl, reg);
64 ath79_gpio_write(ctrl, reg, new_val);
71 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
75 gpiochip_enable_irq(&ctrl->gc, irqd_to_hwirq(data));
76 raw_spin_lock_irqsave(&ctrl->lock, flags);
77 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
78 raw_spin_unlock_irqrestore(&ctrl->lock, flags);
83 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
87 raw_spin_lock_irqsave(&ctrl->lock, flags);
88 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
89 raw_spin_unlock_irqrestore(&ctrl->lock, flags);
90 gpiochip_disable_irq(&ctrl->gc, irqd_to_hwirq(data));
95 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
99 raw_spin_lock_irqsave(&ctrl->lock, flags);
100 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
101 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
102 raw_spin_unlock_irqrestore(&ctrl->lock, flags);
107 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
111 raw_spin_lock_irqsave(&ctrl->lock, flags);
112 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
113 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
114 raw_spin_unlock_irqrestore(&ctrl->lock, flags);
120 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
145 raw_spin_lock_irqsave(&ctrl->lock, flags);
148 ctrl->both_edges |= mask;
149 polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
151 ctrl->both_edges &= ~mask;
159 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
162 ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type);
164 ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity);
168 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
170 raw_spin_unlock_irqrestore(&ctrl->lock, flags);
190 struct ath79_gpio_ctrl *ctrl =
198 raw_spin_lock_irqsave(&ctrl->lock, flags);
200 pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);
203 both_edges = ctrl->both_edges & pending;
205 state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
206 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY,
210 raw_spin_unlock_irqrestore(&ctrl->lock, flags);
230 struct ath79_gpio_ctrl *ctrl;
236 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
237 if (!ctrl)
260 ctrl->base = devm_platform_ioremap_resource(pdev, 0);
261 if (IS_ERR(ctrl->base))
262 return PTR_ERR(ctrl->base);
264 raw_spin_lock_init(&ctrl->lock);
265 err = bgpio_init(&ctrl->gc, dev, 4,
266 ctrl->base + AR71XX_GPIO_REG_IN,
267 ctrl->base + AR71XX_GPIO_REG_SET,
268 ctrl->base + AR71XX_GPIO_REG_CLEAR,
269 oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE,
270 oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL,
277 ctrl->gc.base = 0;
281 girq = &ctrl->gc.irq;
294 return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);