Lines Matching refs:gpio
9 #include <linux/gpio/aspeed.h>
10 #include <linux/gpio/driver.h>
30 #include <linux/gpio/consumer.h>
210 static inline void __iomem *bank_reg(struct aspeed_gpio *gpio,
216 return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
218 return gpio->base + bank->rdata_reg;
220 return gpio->base + bank->val_regs + GPIO_VAL_DIR;
222 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
224 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
226 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
228 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
230 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
232 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1;
234 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2;
236 return gpio->base + bank->tolerance_regs;
238 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0;
240 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1;
267 struct aspeed_gpio *gpio, unsigned int offset)
269 const struct aspeed_bank_props *props = gpio->config->props;
280 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset)
282 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
290 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset)
292 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
300 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset)
302 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
307 static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio,
311 void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0);
312 void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1);
339 static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio,
344 if (!copro_ops || !gpio->cf_copro_bankmap)
346 if (!gpio->cf_copro_bankmap[offset >> 3])
355 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, GPIO_CMDSRC_ARM);
358 gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata));
363 static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio,
368 if (!copro_ops || !gpio->cf_copro_bankmap)
370 if (!gpio->cf_copro_bankmap[offset >> 3])
376 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3,
385 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
388 return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset));
394 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
399 addr = bank_reg(gpio, bank, reg_val);
400 reg = gpio->dcache[GPIO_BANK(offset)];
406 gpio->dcache[GPIO_BANK(offset)] = reg;
414 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
418 raw_spin_lock_irqsave(&gpio->lock, flags);
419 copro = aspeed_gpio_copro_request(gpio, offset);
424 aspeed_gpio_copro_release(gpio, offset);
425 raw_spin_unlock_irqrestore(&gpio->lock, flags);
430 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
432 void __iomem *addr = bank_reg(gpio, bank, reg_dir);
437 if (!have_input(gpio, offset))
440 raw_spin_lock_irqsave(&gpio->lock, flags);
445 copro = aspeed_gpio_copro_request(gpio, offset);
448 aspeed_gpio_copro_release(gpio, offset);
450 raw_spin_unlock_irqrestore(&gpio->lock, flags);
458 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
460 void __iomem *addr = bank_reg(gpio, bank, reg_dir);
465 if (!have_output(gpio, offset))
468 raw_spin_lock_irqsave(&gpio->lock, flags);
473 copro = aspeed_gpio_copro_request(gpio, offset);
478 aspeed_gpio_copro_release(gpio, offset);
479 raw_spin_unlock_irqrestore(&gpio->lock, flags);
486 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
491 if (!have_input(gpio, offset))
494 if (!have_output(gpio, offset))
497 raw_spin_lock_irqsave(&gpio->lock, flags);
499 val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset);
501 raw_spin_unlock_irqrestore(&gpio->lock, flags);
507 struct aspeed_gpio **gpio,
521 *gpio = internal;
531 struct aspeed_gpio *gpio;
538 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
542 status_addr = bank_reg(gpio, bank, reg_irq_status);
544 raw_spin_lock_irqsave(&gpio->lock, flags);
545 copro = aspeed_gpio_copro_request(gpio, offset);
550 aspeed_gpio_copro_release(gpio, offset);
551 raw_spin_unlock_irqrestore(&gpio->lock, flags);
557 struct aspeed_gpio *gpio;
564 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
568 addr = bank_reg(gpio, bank, reg_irq_enable);
572 gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d));
574 raw_spin_lock_irqsave(&gpio->lock, flags);
575 copro = aspeed_gpio_copro_request(gpio, offset);
585 aspeed_gpio_copro_release(gpio, offset);
586 raw_spin_unlock_irqrestore(&gpio->lock, flags);
590 gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(d));
611 struct aspeed_gpio *gpio;
617 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
642 raw_spin_lock_irqsave(&gpio->lock, flags);
643 copro = aspeed_gpio_copro_request(gpio, offset);
645 addr = bank_reg(gpio, bank, reg_irq_type0);
650 addr = bank_reg(gpio, bank, reg_irq_type1);
655 addr = bank_reg(gpio, bank, reg_irq_type2);
661 aspeed_gpio_copro_release(gpio, offset);
662 raw_spin_unlock_irqrestore(&gpio->lock, flags);
676 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
680 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
697 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
698 const struct aspeed_bank_props *props = gpio->config->props;
708 if (i >= gpio->chip.ngpio)
721 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
727 treg = bank_reg(gpio, to_bank(offset), reg_tolerance);
729 raw_spin_lock_irqsave(&gpio->lock, flags);
730 copro = aspeed_gpio_copro_request(gpio, offset);
742 aspeed_gpio_copro_release(gpio, offset);
743 raw_spin_unlock_irqrestore(&gpio->lock, flags);
761 static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs,
768 rate = clk_get_rate(gpio->clk);
784 /* Call under gpio->lock */
785 static int register_allocated_timer(struct aspeed_gpio *gpio,
788 if (WARN(gpio->offset_timer[offset] != 0,
790 offset, gpio->offset_timer[offset]))
793 if (WARN(gpio->timer_users[timer] == UINT_MAX,
797 gpio->offset_timer[offset] = timer;
798 gpio->timer_users[timer]++;
803 /* Call under gpio->lock */
804 static int unregister_allocated_timer(struct aspeed_gpio *gpio,
807 if (WARN(gpio->offset_timer[offset] == 0,
811 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0,
813 gpio->offset_timer[offset]))
816 gpio->timer_users[gpio->offset_timer[offset]]--;
817 gpio->offset_timer[offset] = 0;
822 /* Call under gpio->lock */
823 static inline bool timer_allocation_registered(struct aspeed_gpio *gpio,
826 return gpio->offset_timer[offset] > 0;
829 /* Call under gpio->lock */
830 static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset,
841 addr = bank_reg(gpio, bank, reg_debounce_sel1);
845 addr = bank_reg(gpio, bank, reg_debounce_sel2);
853 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
859 if (!gpio->clk)
862 rc = usecs_to_cycles(gpio, usecs, &requested_cycles);
865 usecs, clk_get_rate(gpio->clk), rc);
869 raw_spin_lock_irqsave(&gpio->lock, flags);
871 if (timer_allocation_registered(gpio, offset)) {
872 rc = unregister_allocated_timer(gpio, offset);
881 cycles = ioread32(gpio->base + debounce_timers[i]);
893 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) {
894 if (gpio->timer_users[j] == 0)
898 if (j == ARRAY_SIZE(gpio->timer_users)) {
911 configure_timer(gpio, offset, 0);
917 iowrite32(requested_cycles, gpio->base + debounce_timers[i]);
925 register_allocated_timer(gpio, offset, i);
926 configure_timer(gpio, offset, i);
929 raw_spin_unlock_irqrestore(&gpio->lock, flags);
936 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
940 raw_spin_lock_irqsave(&gpio->lock, flags);
942 rc = unregister_allocated_timer(gpio, offset);
944 configure_timer(gpio, offset, 0);
946 raw_spin_unlock_irqrestore(&gpio->lock, flags);
954 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
956 if (!have_debounce(gpio, offset))
1015 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
1020 if (!gpio->cf_copro_bankmap)
1021 gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL);
1022 if (!gpio->cf_copro_bankmap)
1024 if (offset < 0 || offset > gpio->chip.ngpio)
1028 raw_spin_lock_irqsave(&gpio->lock, flags);
1031 if (gpio->cf_copro_bankmap[bindex] == 0xff) {
1035 gpio->cf_copro_bankmap[bindex]++;
1038 if (gpio->cf_copro_bankmap[bindex] == 1)
1039 aspeed_gpio_change_cmd_source(gpio, bank, bindex,
1049 raw_spin_unlock_irqrestore(&gpio->lock, flags);
1061 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
1066 if (!gpio->cf_copro_bankmap)
1069 if (offset < 0 || offset > gpio->chip.ngpio)
1073 raw_spin_lock_irqsave(&gpio->lock, flags);
1076 if (gpio->cf_copro_bankmap[bindex] == 0) {
1080 gpio->cf_copro_bankmap[bindex]--;
1083 if (gpio->cf_copro_bankmap[bindex] == 0)
1084 aspeed_gpio_change_cmd_source(gpio, bank, bindex,
1087 raw_spin_unlock_irqrestore(&gpio->lock, flags);
1095 struct aspeed_gpio *gpio;
1099 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
1103 seq_printf(p, dev_name(gpio->dev));
1163 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
1164 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
1165 { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, },
1174 struct aspeed_gpio *gpio;
1178 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
1179 if (!gpio)
1182 gpio->base = devm_platform_ioremap_resource(pdev, 0);
1183 if (IS_ERR(gpio->base))
1184 return PTR_ERR(gpio->base);
1186 gpio->dev = &pdev->dev;
1188 raw_spin_lock_init(&gpio->lock);
1194 gpio->clk = of_clk_get(pdev->dev.of_node, 0);
1195 if (IS_ERR(gpio->clk)) {
1198 gpio->clk = NULL;
1201 gpio->config = gpio_id->data;
1203 gpio->chip.parent = &pdev->dev;
1205 gpio->chip.ngpio = (u16) ngpio;
1207 gpio->chip.ngpio = gpio->config->nr_gpios;
1208 gpio->chip.direction_input = aspeed_gpio_dir_in;
1209 gpio->chip.direction_output = aspeed_gpio_dir_out;
1210 gpio->chip.get_direction = aspeed_gpio_get_direction;
1211 gpio->chip.request = aspeed_gpio_request;
1212 gpio->chip.free = aspeed_gpio_free;
1213 gpio->chip.get = aspeed_gpio_get;
1214 gpio->chip.set = aspeed_gpio_set;
1215 gpio->chip.set_config = aspeed_gpio_set_config;
1216 gpio->chip.label = dev_name(&pdev->dev);
1217 gpio->chip.base = -1;
1220 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
1221 gpio->dcache = devm_kcalloc(&pdev->dev,
1223 if (!gpio->dcache)
1232 void __iomem *addr = bank_reg(gpio, bank, reg_rdata);
1233 gpio->dcache[i] = ioread32(addr);
1234 aspeed_gpio_change_cmd_source(gpio, bank, 0, GPIO_CMDSRC_ARM);
1235 aspeed_gpio_change_cmd_source(gpio, bank, 1, GPIO_CMDSRC_ARM);
1236 aspeed_gpio_change_cmd_source(gpio, bank, 2, GPIO_CMDSRC_ARM);
1237 aspeed_gpio_change_cmd_source(gpio, bank, 3, GPIO_CMDSRC_ARM);
1244 gpio->irq = irq;
1245 girq = &gpio->chip.irq;
1253 girq->parents[0] = gpio->irq;
1258 gpio->offset_timer =
1259 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL);
1260 if (!gpio->offset_timer)
1263 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);