Lines Matching refs:base
59 void __iomem *base;
216 return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
218 return gpio->base + bank->rdata_reg;
220 return gpio->base + bank->val_regs + GPIO_VAL_DIR;
222 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
224 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
226 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
228 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
230 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
232 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1;
234 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2;
236 return gpio->base + bank->tolerance_regs;
238 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0;
240 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1;
753 return pinctrl_gpio_request(chip->base + offset);
758 pinctrl_gpio_free(chip->base + offset);
881 cycles = ioread32(gpio->base + debounce_timers[i]);
917 iowrite32(requested_cycles, gpio->base + debounce_timers[i]);
976 return pinctrl_gpio_set_config(chip->base + offset, config);
1182 gpio->base = devm_platform_ioremap_resource(pdev, 0);
1183 if (IS_ERR(gpio->base))
1184 return PTR_ERR(gpio->base);
1217 gpio->chip.base = -1;