Lines Matching refs:tx
48 * written through the tx.channel pointer, while the second is only written
62 } tx;
102 u32 tx = tegra_ivc_header_read_field(map, tx.count);
115 if (tx - rx > ivc->num_frames)
118 return tx == rx;
123 u32 tx = tegra_ivc_header_read_field(map, tx.count);
130 return tx - rx >= ivc->num_frames;
135 u32 tx = tegra_ivc_header_read_field(map, tx.count);
144 return tx - rx;
149 unsigned int count = tegra_ivc_header_read_field(&ivc->tx.map, tx.count);
151 tegra_ivc_header_write_field(&ivc->tx.map, tx.count, count + 1);
153 if (ivc->tx.position == ivc->num_frames - 1)
154 ivc->tx.position = 0;
156 ivc->tx.position++;
173 unsigned int offset = offsetof(struct tegra_ivc_header, tx.count);
177 * tx.channel->state is set locally, so it is not synchronized with
184 state = tegra_ivc_header_read_field(&ivc->tx.map, tx.state);
211 state = tegra_ivc_header_read_field(&ivc->tx.map, tx.state);
215 if (!tegra_ivc_full(ivc, &ivc->tx.map))
218 tegra_ivc_invalidate(ivc, ivc->tx.phys + offset);
220 if (tegra_ivc_full(ivc, &ivc->tx.map))
306 unsigned int tx = offsetof(struct tegra_ivc_header, tx.count);
324 * ivc->tx.position.
333 tegra_ivc_invalidate(ivc, ivc->rx.phys + tx);
342 /* directly poke at the next frame to be tx'ed */
351 return tegra_ivc_frame_virt(ivc, &ivc->tx.map, ivc->tx.position, map);
355 /* advance the tx buffer */
358 unsigned int tx = offsetof(struct tegra_ivc_header, tx.count);
366 tegra_ivc_flush_frame(ivc, ivc->tx.phys, ivc->tx.position, 0,
371 * ivc->tx.position.
376 tegra_ivc_flush(ivc, ivc->tx.phys + tx);
379 * Ensure our write to ivc->tx.position occurs before our read from
389 tegra_ivc_invalidate(ivc, ivc->tx.phys + rx);
391 if (tegra_ivc_available(ivc, &ivc->tx.map) == 1)
400 unsigned int offset = offsetof(struct tegra_ivc_header, tx.count);
402 tegra_ivc_header_write_field(&ivc->tx.map, tx.state, TEGRA_IVC_STATE_SYNC);
403 tegra_ivc_flush(ivc, ivc->tx.phys + offset);
430 unsigned int offset = offsetof(struct tegra_ivc_header, tx.count);
435 rx_state = tegra_ivc_header_read_field(&ivc->rx.map, tx.state);
436 tx_state = tegra_ivc_header_read_field(&ivc->tx.map, tx.state);
439 offset = offsetof(struct tegra_ivc_header, tx.count);
443 * clearing tx.channel.
448 * Reset tx.channel counters. The remote end is in the SYNC
452 tegra_ivc_header_write_field(&ivc->tx.map, tx.count, 0);
455 ivc->tx.position = 0;
468 tegra_ivc_header_write_field(&ivc->tx.map, tx.state, TEGRA_IVC_STATE_ACK);
469 tegra_ivc_flush(ivc, ivc->tx.phys + offset);
478 offset = offsetof(struct tegra_ivc_header, tx.count);
487 * Reset tx.channel counters. The remote end is in the ACK
491 tegra_ivc_header_write_field(&ivc->tx.map, tx.count, 0);
494 ivc->tx.position = 0;
508 tegra_ivc_header_write_field(&ivc->tx.map, tx.state, TEGRA_IVC_STATE_ESTABLISHED);
509 tegra_ivc_flush(ivc, ivc->tx.phys + offset);
517 offset = offsetof(struct tegra_ivc_header, tx.count);
522 * peer state before storing to tx.channel.
532 tegra_ivc_header_write_field(&ivc->tx.map, tx.state, TEGRA_IVC_STATE_ESTABLISHED);
533 tegra_ivc_flush(ivc, ivc->tx.phys + offset);
574 static int tegra_ivc_check_params(unsigned long rx, unsigned long tx,
577 BUILD_BUG_ON(!IS_ALIGNED(offsetof(struct tegra_ivc_header, tx.count),
603 if (!IS_ALIGNED(tx, TEGRA_IVC_ALIGN)) {
604 pr_err("IVC channel start not aligned: %#lx\n", tx);
608 if (rx < tx) {
609 if (rx + frame_size * num_frames > tx) {
611 rx, frame_size * num_frames, tx);
615 if (tx + frame_size * num_frames > rx) {
617 tx, frame_size * num_frames, rx);
647 dma_addr_t rx_phys, const struct iosys_map *tx, dma_addr_t tx_phys,
665 err = tegra_ivc_check_params(iosys_map_get_address(rx), iosys_map_get_address(tx),
678 ivc->tx.phys = dma_map_single(peer, iosys_map_get_vaddr(tx), queue_size,
680 if (dma_mapping_error(peer, ivc->tx.phys)) {
687 ivc->tx.phys = tx_phys;
691 iosys_map_copy(&ivc->tx.map, tx);
702 ivc->tx.position = 0;
717 dma_unmap_single(ivc->peer, ivc->tx.phys, size,