Lines Matching refs:rx
49 * through the rx.channel pointer. This delineates ownership of the cache
68 } rx;
103 u32 rx = tegra_ivc_header_read_field(map, rx.count);
115 if (tx - rx > ivc->num_frames)
118 return tx == rx;
124 u32 rx = tegra_ivc_header_read_field(map, rx.count);
130 return tx - rx >= ivc->num_frames;
136 u32 rx = tegra_ivc_header_read_field(map, rx.count);
144 return tx - rx;
161 unsigned int count = tegra_ivc_header_read_field(&ivc->rx.map, rx.count);
163 tegra_ivc_header_write_field(&ivc->rx.map, rx.count, count + 1);
165 if (ivc->rx.position == ivc->num_frames - 1)
166 ivc->rx.position = 0;
168 ivc->rx.position++;
181 * asynchronous transition of rx.channel->state to
195 if (!tegra_ivc_empty(ivc, &ivc->rx.map))
198 tegra_ivc_invalidate(ivc, ivc->rx.phys + offset);
200 if (tegra_ivc_empty(ivc, &ivc->rx.map))
208 unsigned int offset = offsetof(struct tegra_ivc_header, rx.count);
278 /* directly peek at the next frame rx'ed */
291 * Order observation of ivc->rx.position potentially indicating new
296 tegra_ivc_invalidate_frame(ivc, ivc->rx.phys, ivc->rx.position, 0,
299 return tegra_ivc_frame_virt(ivc, &ivc->rx.map, ivc->rx.position, map);
305 unsigned int rx = offsetof(struct tegra_ivc_header, rx.count);
320 tegra_ivc_flush(ivc, ivc->rx.phys + rx);
323 * Ensure our write to ivc->rx.position occurs before our read from
333 tegra_ivc_invalidate(ivc, ivc->rx.phys + tx);
335 if (tegra_ivc_available(ivc, &ivc->rx.map) == ivc->num_frames - 1)
359 unsigned int rx = offsetof(struct tegra_ivc_header, rx.count);
380 * ivc->rx.position.
389 tegra_ivc_invalidate(ivc, ivc->tx.phys + rx);
434 tegra_ivc_invalidate(ivc, ivc->rx.phys + offset);
435 rx_state = tegra_ivc_header_read_field(&ivc->rx.map, tx.state);
453 tegra_ivc_header_write_field(&ivc->rx.map, rx.count, 0);
456 ivc->rx.position = 0;
492 tegra_ivc_header_write_field(&ivc->rx.map, rx.count, 0);
495 ivc->rx.position = 0;
574 static int tegra_ivc_check_params(unsigned long rx, unsigned long tx,
579 BUILD_BUG_ON(!IS_ALIGNED(offsetof(struct tegra_ivc_header, rx.count),
598 if (!IS_ALIGNED(rx, TEGRA_IVC_ALIGN)) {
599 pr_err("IVC channel start not aligned: %#lx\n", rx);
608 if (rx < tx) {
609 if (rx + frame_size * num_frames > tx) {
611 rx, frame_size * num_frames, tx);
615 if (tx + frame_size * num_frames > rx) {
617 tx, frame_size * num_frames, rx);
646 int tegra_ivc_init(struct tegra_ivc *ivc, struct device *peer, const struct iosys_map *rx,
665 err = tegra_ivc_check_params(iosys_map_get_address(rx), iosys_map_get_address(tx),
673 ivc->rx.phys = dma_map_single(peer, iosys_map_get_vaddr(rx), queue_size,
675 if (dma_mapping_error(peer, ivc->rx.phys))
681 dma_unmap_single(peer, ivc->rx.phys, queue_size,
686 ivc->rx.phys = rx_phys;
690 iosys_map_copy(&ivc->rx.map, rx);
703 ivc->rx.position = 0;
715 dma_unmap_single(ivc->peer, ivc->rx.phys, size,