Lines Matching refs:reg_write
572 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
599 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
625 reg_write(ohci, OHCI1394_PhyControl,
717 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
742 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1079 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1080 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1257 reg_write(ohci, COMMAND_PTR(ctx->regs),
1259 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1260 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1307 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1454 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1613 reg_write(ohci, OHCI1394_CSRData, lock_data);
1614 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1615 reg_write(ohci, OHCI1394_CSRControl, sel);
1809 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1957 reg_write(ohci, OHCI1394_LinkControlSet,
2062 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2091 reg_write(ohci, OHCI1394_BusOptions,
2094 reg_write(ohci, OHCI1394_ConfigROMhdr,
2099 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
2100 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
2131 reg_write(ohci, OHCI1394_IntEventClear,
2152 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2164 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2180 reg_write(ohci, OHCI1394_IntEventClear,
2189 reg_write(ohci, OHCI1394_LinkControlSet,
2222 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2288 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2291 reg_write(ohci, OHCI1394_HCControlClear,
2345 reg_write(ohci, OHCI1394_HCControlSet,
2371 reg_write(ohci, OHCI1394_HCControlClear,
2374 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2375 reg_write(ohci, OHCI1394_LinkControlSet,
2379 reg_write(ohci, OHCI1394_ATRetries,
2389 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
2394 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2400 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2402 reg_write(ohci, OHCI1394_FairnessControl, 0);
2405 reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16);
2406 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2407 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2455 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2456 reg_write(ohci, OHCI1394_BusOptions,
2458 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2460 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2474 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2476 reg_write(ohci, OHCI1394_HCControlSet,
2480 reg_write(ohci, OHCI1394_LinkControlSet,
2560 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2657 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2659 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2727 reg_write(ohci, OHCI1394_LinkControlClear,
2737 reg_write(ohci, OHCI1394_LinkControlSet,
2746 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2751 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2752 reg_write(ohci, OHCI1394_IntEventSet,
2767 reg_write(ohci, OHCI1394_ATRetries, value);
2772 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2981 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2982 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2983 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2984 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
3106 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3107 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
3122 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3123 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
3124 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
3145 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3151 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3520 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3716 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3719 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3727 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3734 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3790 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3845 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3846 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));