Lines Matching defs:val
66 static void xgene_edac_pcp_rd(struct xgene_edac *edac, u32 reg, u32 *val)
68 *val = readl(edac->pcp_csr + reg);
74 u32 val;
77 val = readl(edac->pcp_csr + reg);
78 val &= ~bits_mask;
79 writel(val, edac->pcp_csr + reg);
86 u32 val;
89 val = readl(edac->pcp_csr + reg);
90 val |= bits_mask;
91 writel(val, edac->pcp_csr + reg);
250 unsigned int val;
281 val = readl(ctx->mcu_csr + MCUGECR);
282 val |= MCU_GECR_DEMANDUCINTREN_MASK |
286 writel(val, ctx->mcu_csr + MCUGECR);
289 val = readl(ctx->mcu_csr + MCUGECR);
290 val &= ~(MCU_GECR_DEMANDUCINTREN_MASK |
294 writel(val, ctx->mcu_csr + MCUGECR);
524 u32 val;
528 val = readl(pg_f + MEMERR_CPU_ICFESR_PAGE_OFFSET);
529 if (!val)
533 ctx->pmd * MAX_CPU_PER_PMD + cpu_idx, val,
534 MEMERR_CPU_ICFESR_ERRWAY_RD(val),
535 MEMERR_CPU_ICFESR_ERRINDEX_RD(val),
536 MEMERR_CPU_ICFESR_ERRINFO_RD(val));
537 if (val & MEMERR_CPU_ICFESR_CERR_MASK)
539 if (val & MEMERR_CPU_ICFESR_MULTCERR_MASK)
541 switch (MEMERR_CPU_ICFESR_ERRTYPE_RD(val)) {
561 writel(val, pg_f + MEMERR_CPU_ICFESR_PAGE_OFFSET);
563 if (val & (MEMERR_CPU_ICFESR_CERR_MASK |
568 val = readl(pg_f + MEMERR_CPU_LSUESR_PAGE_OFFSET);
569 if (!val)
573 ctx->pmd * MAX_CPU_PER_PMD + cpu_idx, val,
574 MEMERR_CPU_LSUESR_ERRWAY_RD(val),
575 MEMERR_CPU_LSUESR_ERRINDEX_RD(val),
576 MEMERR_CPU_LSUESR_ERRINFO_RD(val));
577 if (val & MEMERR_CPU_LSUESR_CERR_MASK)
579 if (val & MEMERR_CPU_LSUESR_MULTCERR_MASK)
581 switch (MEMERR_CPU_LSUESR_ERRTYPE_RD(val)) {
605 writel(val, pg_f + MEMERR_CPU_LSUESR_PAGE_OFFSET);
607 if (val & (MEMERR_CPU_LSUESR_CERR_MASK |
612 val = readl(pg_f + MEMERR_CPU_MMUESR_PAGE_OFFSET);
613 if (!val)
617 ctx->pmd * MAX_CPU_PER_PMD + cpu_idx, val,
618 MEMERR_CPU_MMUESR_ERRWAY_RD(val),
619 MEMERR_CPU_MMUESR_ERRINDEX_RD(val),
620 MEMERR_CPU_MMUESR_ERRINFO_RD(val),
621 val & MEMERR_CPU_MMUESR_ERRREQSTR_LSU_MASK ? "LSU" : "ICF");
622 if (val & MEMERR_CPU_MMUESR_CERR_MASK)
624 if (val & MEMERR_CPU_MMUESR_MULTCERR_MASK)
626 switch (MEMERR_CPU_MMUESR_ERRTYPE_RD(val)) {
654 writel(val, pg_f + MEMERR_CPU_MMUESR_PAGE_OFFSET);
666 u32 val;
670 val = readl(pg_e + MEMERR_L2C_L2ESR_PAGE_OFFSET);
671 if (!val)
677 ctx->pmd, val, val_hi, val_lo);
680 MEMERR_L2C_L2ESR_ERRSYN_RD(val),
681 MEMERR_L2C_L2ESR_ERRWAY_RD(val),
682 MEMERR_L2C_L2ESR_ERRCPU_RD(val),
683 MEMERR_L2C_L2ESR_ERRGROUP_RD(val),
684 MEMERR_L2C_L2ESR_ERRACTION_RD(val));
686 if (val & MEMERR_L2C_L2ESR_ERR_MASK)
688 if (val & MEMERR_L2C_L2ESR_MULTICERR_MASK)
690 if (val & MEMERR_L2C_L2ESR_UCERR_MASK)
692 if (val & MEMERR_L2C_L2ESR_MULTUCERR_MASK)
695 switch (MEMERR_L2C_L2ESR_ERRTYPE_RD(val)) {
711 writel(val, pg_e + MEMERR_L2C_L2ESR_PAGE_OFFSET);
713 if (val & (MEMERR_L2C_L2ESR_ERR_MASK |
716 if (val & (MEMERR_L2C_L2ESR_UCERR_MASK |
723 val = readl(pg_d + CPUX_L2C_L2RTOSR_PAGE_OFFSET);
724 if (val) {
729 ctx->pmd, val, val_hi, val_lo);
730 writel(val, pg_d + CPUX_L2C_L2RTOSR_PAGE_OFFSET);
895 u32 val;
906 rc = regmap_read(edac->efuse_map, 0, &val);
909 if (!xgene_edac_pmd_available(val, pmd)) {
1117 u32 val;
1119 val = readl(ctx->dev_csr + L3C_ECR);
1120 val |= L3C_UCERREN | L3C_CERREN;
1124 val |= L3C_ECR_UCINTREN | L3C_ECR_CINTREN;
1126 val &= ~(L3C_ECR_UCINTREN | L3C_ECR_CINTREN);
1128 writel(val, ctx->dev_csr + L3C_ECR);