Lines Matching defs:baseaddr
301 * @baseaddr: Base address of the DDR controller.
315 void __iomem *baseaddr;
359 base = priv->baseaddr;
414 base = priv->baseaddr;
521 priv->baseaddr + ECC_CLR_OFST);
524 priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
532 writel(0x0, priv->baseaddr + ECC_CLR_OFST);
535 priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
560 regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
578 writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
816 dimm->mtype = p_data->get_mtype(priv->baseaddr);
819 dimm->dtype = p_data->get_dtype(priv->baseaddr);
997 writel(regval, priv->baseaddr + ECC_POISON0_OFST);
1002 writel(regval, priv->baseaddr + ECC_POISON1_OFST);
1014 readl(priv->baseaddr + ECC_POISON0_OFST),
1015 readl(priv->baseaddr + ECC_POISON1_OFST),
1042 (((readl(priv->baseaddr + ECC_CFG1_OFST)) & 0x3) == 0x3)
1053 writel(0, priv->baseaddr + DDRC_SWCTL);
1055 writel(ECC_CEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST);
1057 writel(ECC_UEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST);
1058 writel(1, priv->baseaddr + DDRC_SWCTL);
1149 memtype = readl(priv->baseaddr + CTRL_OFST);
1296 addrmap[index] = readl(priv->baseaddr + addrmap_offset);
1326 void __iomem *baseaddr;
1331 baseaddr = devm_ioremap_resource(&pdev->dev, res);
1332 if (IS_ERR(baseaddr))
1333 return PTR_ERR(baseaddr);
1339 if (!p_data->get_ecc_state(baseaddr)) {
1360 priv->baseaddr = baseaddr;
1397 writel(0x0, baseaddr + ECC_CTRL_OFST);