Lines Matching refs:reg

75 #define DRAM_RULE_ENABLE(reg)	GET_BITFIELD(reg, 0,  0)
76 #define A7MODE(reg)		GET_BITFIELD(reg, 26, 26)
143 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
146 	return GET_BITFIELD(reg, table[interleave].start,
161 #define GET_TOLM(reg)		((GET_BITFIELD(reg, 0,  3) << 28) | 0x3ffffff)
162 #define GET_TOHM(reg)		((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
168 #define SOURCE_ID(reg)		GET_BITFIELD(reg, 9, 11)
170 #define SOURCE_ID_KNL(reg)	GET_BITFIELD(reg, 12, 14)
183 #define TAD_LIMIT(reg)		((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
184 #define TAD_SOCK(reg)		GET_BITFIELD(reg, 10, 11)
185 #define TAD_CH(reg)		GET_BITFIELD(reg,  8,  9)
186 #define TAD_TGT3(reg)		GET_BITFIELD(reg,  6,  7)
187 #define TAD_TGT2(reg)		GET_BITFIELD(reg,  4,  5)
188 #define TAD_TGT1(reg)		GET_BITFIELD(reg,  2,  3)
189 #define TAD_TGT0(reg)		GET_BITFIELD(reg,  0,  1)
203 #define IS_MIRROR_ENABLED(reg)		GET_BITFIELD(reg, 0, 0)
224 #define CHN_IDX_OFFSET(reg)		GET_BITFIELD(reg, 28, 29)
225 #define TAD_OFFSET(reg)			(GET_BITFIELD(reg,  6, 25) << 26)
232 #define IS_RIR_VALID(reg)	GET_BITFIELD(reg, 31, 31)
233 #define RIR_WAY(reg)		GET_BITFIELD(reg, 28, 29)
245 #define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \
246 	GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19))
248 #define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \
249 	GET_BITFIELD(reg,  2, 15) : GET_BITFIELD(reg,  2, 14))
257 #define RANK_ODD_OV(reg)		GET_BITFIELD(reg, 31, 31)
258 #define RANK_ODD_ERR_CNT(reg)		GET_BITFIELD(reg, 16, 30)
259 #define RANK_EVEN_OV(reg)		GET_BITFIELD(reg, 15, 15)
260 #define RANK_EVEN_ERR_CNT(reg)		GET_BITFIELD(reg,  0, 14)
272 #define RANK_ODD_ERR_THRSLD(reg)	GET_BITFIELD(reg, 16, 30)
273 #define RANK_EVEN_ERR_THRSLD(reg)	GET_BITFIELD(reg,  0, 14)
320 	u64		(*rir_limit)(u32 reg);
321 	u64		(*sad_limit)(u32 reg);
322 	u32		(*interleave_mode)(u32 reg);
323 	u32		(*dram_attr)(u32 reg);
802 	u32 reg;
805 	pci_read_config_dword(pvt->pci_sad1, TOLM, &reg);
806 	return GET_TOLM(reg);
811 	u32 reg;
813 	pci_read_config_dword(pvt->pci_sad1, TOHM, &reg);
814 	return GET_TOHM(reg);
819 	u32 reg;
821 	pci_read_config_dword(pvt->pci_br1, TOLM, &reg);
823 	return GET_TOLM(reg);
828 	u32 reg;
830 	pci_read_config_dword(pvt->pci_br1, TOHM, &reg);
832 	return GET_TOHM(reg);
835 static u64 rir_limit(u32 reg)
837 	return ((u64)GET_BITFIELD(reg,  1, 10) << 29) | 0x1fffffff;
840 static u64 sad_limit(u32 reg)
842 	return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff;
845 static u32 interleave_mode(u32 reg)
847 	return GET_BITFIELD(reg, 1, 1);
850 static u32 dram_attr(u32 reg)
852 	return GET_BITFIELD(reg, 2, 3);
855 static u64 knl_sad_limit(u32 reg)
857 	return (GET_BITFIELD(reg, 7, 26) << 26) | 0x3ffffff;
860 static u32 knl_interleave_mode(u32 reg)
862 	return GET_BITFIELD(reg, 1, 2);
869 static const char *get_intlv_mode_str(u32 reg, enum type t)
872 		return knl_intlv_mode[knl_interleave_mode(reg)];
874 		return interleave_mode(reg) ? "[8:6]" : "[8:6]XOR[18:16]";
877 static u32 dram_attr_knl(u32 reg)
879 	return GET_BITFIELD(reg, 3, 4);
885 	u32 reg;
890 				      &reg);
891 		if (GET_BITFIELD(reg, 11, 11))
904 	u32 reg;
912 			      HASWELL_DDRCRCLKCONTROLS, &reg);
914 	if (GET_BITFIELD(reg, 16, 16))
917 	pci_read_config_dword(pvt->pci_ta, MCMTR, &reg);
918 	if (GET_BITFIELD(reg, 14, 14)) {
988 	u32 reg;
989 	pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, &reg);
990 	return GET_BITFIELD(reg, 0, 2);
995 	u32 reg;
997 	pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
998 	return GET_BITFIELD(reg, 0, 3);
1003 	u32 reg;
1005 	pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
1006 	return GET_BITFIELD(reg, 0, 2);
1045 	u32 reg;
1047 	pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, &reg);
1048 	return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
1054 	u32 reg;
1056 	pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, &reg);
1057 	rc = GET_BITFIELD(reg, 26, 31);
1058 	pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, &reg);
1059 	rc = ((reg << 6) | rc) << 26;
1066 	u32 reg;
1068 	pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, &reg);
1069 	return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
1084 static u64 haswell_rir_limit(u32 reg)
1086 	return (((u64)GET_BITFIELD(reg,  1, 11) + 1) << 29) - 1;
1233 static u32 knl_get_edc_route(int entry, u32 reg)
1236 	return GET_BITFIELD(reg, entry*3, (entry*3)+2);
1256 static u32 knl_get_mc_route(int entry, u32 reg)
1262 	mc = GET_BITFIELD(reg, entry*3, (entry*3)+2);
1263 	chan = GET_BITFIELD(reg, (entry*2) + 18, (entry*2) + 18 + 1);
1272 static void knl_show_edc_route(u32 reg, char *s)
1277 		s[i*2] = knl_get_edc_route(i, reg) + '0';
1288 static void knl_show_mc_route(u32 reg, char *s)
1293 		s[i*2] = knl_get_mc_route(i, reg) + '0';
1304 #define KNL_EDRAM(reg) GET_BITFIELD(reg, 29, 29)
1307 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1310 #define KNL_EDRAM_ONLY(reg) GET_BITFIELD(reg, 29, 29)
1313 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1316 #define KNL_MOD3(reg) GET_BITFIELD(reg, 27, 27)
1572 	u32 reg;
1576 		pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, &reg);
1578 		pci_read_config_dword(pvt->pci_br0, SAD_TARGET, &reg);
1581 		pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg);
1583 		pvt->sbridge_dev->source_id = SOURCE_ID(reg);
1692 	u32 reg;
1716 			if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, &reg)) {
1720 			pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21);
1721 			if (GET_BITFIELD(reg, 28, 28)) {
1727 		if (pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg)) {
1731 		if (IS_MIRROR_ENABLED(reg)) {
1769 	u32 reg;
1804 				      &reg);
1805 		limit = pvt->info.sad_limit(reg);
1807 		if (!DRAM_RULE_ENABLE(reg))
1815 		edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
1817 			 show_dram_attr(pvt->info.dram_attr(reg)),
1820 			 get_intlv_mode_str(reg, pvt->info.type),
1821 			 reg);
1825 				      &reg);
1826 		sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1828 			u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
1845 		pci_read_config_dword(pvt->pci_ha, tad_dram_rule[n_tads], &reg);
1846 		limit = TAD_LIMIT(reg);
1852 		edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
1855 			 (u32)(1 << TAD_SOCK(reg)),
1856 			 (u32)TAD_CH(reg) + 1,
1857 			 (u32)TAD_TGT0(reg),
1858 			 (u32)TAD_TGT1(reg),
1859 			 (u32)TAD_TGT2(reg),
1860 			 (u32)TAD_TGT3(reg),
1861 			 reg);
1874 					      &reg);
1875 			tmp_mb = TAD_OFFSET(reg) >> 20;
1877 			edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
1881 				 reg);
1894 					      &reg);
1896 			if (!IS_RIR_VALID(reg))
1899 			tmp_mb = pvt->info.rir_limit(reg) >> 20;
1900 			rir_way = 1 << RIR_WAY(reg);
1902 			edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
1907 				 reg);
1912 						      &reg);
1913 				tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6;
1916 				edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
1920 					 (u32)RIR_RNK_TGT(pvt->info.type, reg),
1921 					 reg);
2045 	u32			reg, dram_rule;
2075 				      &reg);
2077 		if (!DRAM_RULE_ENABLE(reg))
2080 		limit = pvt->info.sad_limit(reg);
2093 	dram_rule = reg;
2098 			      &reg);
2101 		sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
2103 			u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
2157 		pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2163 			pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, &reg);
2164 			shiftup = GET_BITFIELD(reg, 22, 22);
2172 		pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2200 		pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], &reg);
2201 		limit = TAD_LIMIT(reg);
2215 	ch_way = TAD_CH(reg) + 1;
2216 	sck_way = TAD_SOCK(reg);
2232 		base_ch = TAD_TGT0(reg);
2235 		base_ch = TAD_TGT1(reg);
2238 		base_ch = TAD_TGT2(reg);
2241 		base_ch = TAD_TGT3(reg);
2305 		pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], &reg);
2307 		if (!IS_RIR_VALID(reg))
2310 		limit = pvt->info.rir_limit(reg);
2316 			 1 << RIR_WAY(reg));
2325 	rir_way = RIR_WAY(reg);
2333 	pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], &reg);
2334 	*rank = RIR_RNK_TGT(pvt->info.type, reg);
2346 		rank_addr -= RIR_OFFSET(pvt->info.type, reg);
2373 	u32 reg, channel = GET_BITFIELD(m->status, 0, 3);
2404 	pci_read_config_dword(pci_ha, tad_dram_rule[0], &reg);
2405 	tad0 = m->addr <= TAD_LIMIT(reg);