Lines Matching refs:pvt
318 u64 (*get_tolm)(struct sbridge_pvt *pvt);
319 u64 (*get_tohm)(struct sbridge_pvt *pvt);
328 u8 (*get_node_id)(struct sbridge_pvt *pvt);
330 enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt);
331 enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
800 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
805 pci_read_config_dword(pvt->pci_sad1, TOLM, ®);
809 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
813 pci_read_config_dword(pvt->pci_sad1, TOHM, ®);
817 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
821 pci_read_config_dword(pvt->pci_br1, TOLM, ®);
826 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
830 pci_read_config_dword(pvt->pci_br1, TOHM, ®);
883 static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
888 if (pvt->pci_ddrio) {
889 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
902 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
908 if (!pvt->pci_ddrio)
911 pci_read_config_dword(pvt->pci_ddrio,
917 pci_read_config_dword(pvt->pci_ta, MCMTR, ®);
934 static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr)
940 static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
965 static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
974 static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr)
980 static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt)
986 static u8 get_node_id(struct sbridge_pvt *pvt)
989 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®);
993 static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
997 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®);
1001 static u8 knl_get_node_id(struct sbridge_pvt *pvt)
1005 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®);
1043 static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
1047 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®);
1051 static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
1056 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®);
1058 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®);
1064 static u64 knl_get_tolm(struct sbridge_pvt *pvt)
1068 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, ®);
1072 static u64 knl_get_tohm(struct sbridge_pvt *pvt)
1077 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, ®_lo);
1078 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, ®_hi);
1141 * @pvt: driver private data
1152 static int knl_get_tad(const struct sbridge_pvt *pvt,
1165 pci_mc = pvt->knl.pci_mc0;
1168 pci_mc = pvt->knl.pci_mc1;
1346 static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes)
1373 pci_read_config_dword(pvt->knl.pci_cha[i],
1399 pci_read_config_dword(pvt->knl.pci_cha[i],
1422 for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) {
1426 pci_read_config_dword(pvt->pci_sad0,
1427 pvt->info.dram_rule[sad_rule], &dram_rule);
1434 sad_limit = pvt->info.sad_limit(dram_rule)+1;
1436 pci_read_config_dword(pvt->pci_sad0,
1437 pvt->info.interleave_list[sad_rule], &interleave_reg);
1443 first_pkg = sad_pkg(pvt->info.interleave_pkg,
1446 pkg = sad_pkg(pvt->info.interleave_pkg,
1490 if (knl_get_tad(pvt,
1571 struct sbridge_pvt *pvt = mci->pvt_info;
1574 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||
1575 pvt->info.type == KNIGHTS_LANDING)
1576 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®);
1578 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®);
1580 if (pvt->info.type == KNIGHTS_LANDING)
1581 pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg);
1583 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
1590 struct sbridge_pvt *pvt = mci->pvt_info;
1591 int channels = pvt->info.type == KNIGHTS_LANDING ? KNL_MAX_CHANNELS
1598 mtype = pvt->info.get_memory_type(pvt);
1616 if (pvt->info.type == KNIGHTS_LANDING) {
1618 if (!pvt->knl.pci_channel[i])
1622 if (!pvt->pci_tad[i])
1624 pci_read_config_dword(pvt->pci_tad[i], 0x8c, &amap);
1629 if (pvt->info.type == KNIGHTS_LANDING) {
1630 pci_read_config_dword(pvt->knl.pci_channel[i],
1633 pci_read_config_dword(pvt->pci_tad[i],
1639 if (!IS_ECC_ENABLED(pvt->info.mcmtr)) {
1641 pvt->sbridge_dev->source_id,
1642 pvt->sbridge_dev->dom, i);
1645 pvt->channel[i].dimms++;
1647 ranks = numrank(pvt->info.type, mtr);
1649 if (pvt->info.type == KNIGHTS_LANDING) {
1663 pvt->sbridge_dev->mc, pvt->sbridge_dev->dom, i, j,
1669 dimm->dtype = pvt->info.get_width(pvt, mtr);
1672 pvt->channel[i].dimm[j].rowbits = order_base_2(rows);
1673 pvt->channel[i].dimm[j].colbits = order_base_2(cols);
1674 pvt->channel[i].dimm[j].bank_xor_enable =
1675 GET_BITFIELD(pvt->info.mcmtr, 9, 9);
1676 pvt->channel[i].dimm[j].amap_fine = GET_BITFIELD(amap, 0, 0);
1679 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom, i, j);
1689 struct sbridge_pvt *pvt = mci->pvt_info;
1694 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
1696 pvt->sbridge_dev->mc,
1697 pvt->sbridge_dev->node_id,
1698 pvt->sbridge_dev->source_id);
1703 if (pvt->info.type == KNIGHTS_LANDING) {
1705 pvt->mirror_mode = NON_MIRRORING;
1706 pvt->is_cur_addr_mirrored = false;
1708 if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0)
1710 if (pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr)) {
1715 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
1716 if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®)) {
1720 pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21);
1722 pvt->mirror_mode = ADDR_RANGE_MIRRORING;
1727 if (pci_read_config_dword(pvt->pci_ras, RASENABLES, ®)) {
1732 pvt->mirror_mode = FULL_MIRRORING;
1735 pvt->mirror_mode = NON_MIRRORING;
1740 if (pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr)) {
1744 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
1747 pvt->is_lockstep = true;
1751 pvt->is_lockstep = false;
1753 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
1755 pvt->is_close_pg = true;
1758 pvt->is_close_pg = false;
1767 struct sbridge_pvt *pvt = mci->pvt_info;
1779 pvt->tolm = pvt->info.get_tolm(pvt);
1780 tmp_mb = (1 + pvt->tolm) >> 20;
1784 gb, (mb*1000)/1024, (u64)pvt->tolm);
1787 pvt->tohm = pvt->info.get_tohm(pvt);
1788 tmp_mb = (1 + pvt->tohm) >> 20;
1792 gb, (mb*1000)/1024, (u64)pvt->tohm);
1801 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1803 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1805 limit = pvt->info.sad_limit(reg);
1817 show_dram_attr(pvt->info.dram_attr(reg)),
1820 get_intlv_mode_str(reg, pvt->info.type),
1824 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1826 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1828 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
1837 if (pvt->info.type == KNIGHTS_LANDING)
1845 pci_read_config_dword(pvt->pci_ha, tad_dram_rule[n_tads], ®);
1869 if (!pvt->channel[i].dimms)
1872 pci_read_config_dword(pvt->pci_tad[i],
1889 if (!pvt->channel[i].dimms)
1892 pci_read_config_dword(pvt->pci_tad[i],
1899 tmp_mb = pvt->info.rir_limit(reg) >> 20;
1910 pci_read_config_dword(pvt->pci_tad[i],
1913 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6;
1920 (u32)RIR_RNK_TGT(pvt->info.type, reg),
1982 struct sbridge_pvt *pvt;
1987 pvt = mci->pvt_info;
1988 amap_fine = pvt->channel[ch].dimm[dimmno].amap_fine;
1990 rowbits = pvt->channel[ch].dimm[dimmno].rowbits;
1991 colbits = pvt->channel[ch].dimm[dimmno].colbits;
1992 bank_xor_enable = pvt->channel[ch].dimm[dimmno].bank_xor_enable;
1994 if (pvt->is_lockstep) {
2000 if (pvt->is_close_pg) {
2039 struct sbridge_pvt *pvt = mci->pvt_info;
2061 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
2065 if (addr >= (u64)pvt->tohm) {
2073 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
2074 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
2080 limit = pvt->info.sad_limit(reg);
2089 if (n_sads == pvt->info.max_sad) {
2094 *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule));
2095 interleave_mode = pvt->info.interleave_mode(dram_rule);
2097 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
2100 if (pvt->info.type == SANDY_BRIDGE) {
2101 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
2103 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
2111 pvt->sbridge_dev->mc,
2140 } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
2157 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2163 pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®);
2172 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2192 pvt = mci->pvt_info;
2198 pci_ha = pvt->pci_ha;
2222 if (pvt->is_chan_hash)
2249 pci_read_config_dword(pvt->pci_tad[base_ch], tad_ch_nilv_offset[n_tads], &tad_offset);
2251 if (pvt->mirror_mode == FULL_MIRRORING ||
2252 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && n_tads == 0)) {
2264 pvt->is_cur_addr_mirrored = true;
2267 pvt->is_cur_addr_mirrored = false;
2270 if (pvt->is_lockstep)
2305 pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], ®);
2310 limit = pvt->info.rir_limit(reg);
2327 if (pvt->is_close_pg)
2333 pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], ®);
2334 *rank = RIR_RNK_TGT(pvt->info.type, reg);
2336 if (pvt->info.type == BROADWELL) {
2337 if (pvt->is_close_pg)
2346 rank_addr -= RIR_OFFSET(pvt->info.type, reg);
2348 mtype = pvt->info.get_memory_type(pvt);
2375 struct sbridge_pvt *pvt;
2384 pvt = mci->pvt_info;
2385 if (!pvt->info.get_ha) {
2389 *ha = pvt->info.get_ha(m->bank);
2402 pvt = new_mci->pvt_info;
2403 pci_ha = pvt->pci_ha;
2408 if (pvt->mirror_mode == FULL_MIRRORING ||
2409 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && tad0)) {
2411 pvt->is_cur_addr_mirrored = true;
2413 pvt->is_cur_addr_mirrored = false;
2416 if (pvt->is_lockstep)
2618 struct sbridge_pvt *pvt = mci->pvt_info;
2630 pvt->pci_sad0 = pdev;
2633 pvt->pci_sad1 = pdev;
2636 pvt->pci_br0 = pdev;
2639 pvt->pci_ha = pdev;
2642 pvt->pci_ta = pdev;
2645 pvt->pci_ras = pdev;
2653 pvt->pci_tad[id] = pdev;
2658 pvt->pci_ddrio = pdev;
2671 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha ||
2672 !pvt->pci_ras || !pvt->pci_ta)
2692 struct sbridge_pvt *pvt = mci->pvt_info;
2705 pvt->pci_ha = pdev;
2709 pvt->pci_ta = pdev;
2713 pvt->pci_ras = pdev;
2725 pvt->pci_tad[id] = pdev;
2730 pvt->pci_ddrio = pdev;
2733 pvt->pci_ddrio = pdev;
2736 pvt->pci_sad0 = pdev;
2739 pvt->pci_br0 = pdev;
2742 pvt->pci_br1 = pdev;
2755 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_br0 ||
2756 !pvt->pci_br1 || !pvt->pci_ras || !pvt->pci_ta)
2778 struct sbridge_pvt *pvt = mci->pvt_info;
2784 if (pvt->info.pci_vtd == NULL)
2786 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2797 pvt->pci_sad0 = pdev;
2800 pvt->pci_sad1 = pdev;
2804 pvt->pci_ha = pdev;
2808 pvt->pci_ta = pdev;
2812 pvt->pci_ras = pdev;
2824 pvt->pci_tad[id] = pdev;
2832 if (!pvt->pci_ddrio)
2833 pvt->pci_ddrio = pdev;
2846 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 ||
2847 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
2863 struct sbridge_pvt *pvt = mci->pvt_info;
2869 if (pvt->info.pci_vtd == NULL)
2871 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2882 pvt->pci_sad0 = pdev;
2885 pvt->pci_sad1 = pdev;
2889 pvt->pci_ha = pdev;
2893 pvt->pci_ta = pdev;
2897 pvt->pci_ras = pdev;
2909 pvt->pci_tad[id] = pdev;
2914 pvt->pci_ddrio = pdev;
2927 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 ||
2928 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
2944 struct sbridge_pvt *pvt = mci->pvt_info;
2963 pvt->knl.pci_mc0 = pdev;
2965 pvt->knl.pci_mc1 = pdev;
2975 pvt->pci_sad0 = pdev;
2979 pvt->pci_sad1 = pdev;
2995 WARN_ON(pvt->knl.pci_cha[devidx] != NULL);
2997 pvt->knl.pci_cha[devidx] = pdev;
3020 WARN_ON(pvt->knl.pci_channel[devidx] != NULL);
3021 pvt->knl.pci_channel[devidx] = pdev;
3025 pvt->knl.pci_mc_info = pdev;
3029 pvt->pci_ta = pdev;
3039 if (!pvt->knl.pci_mc0 || !pvt->knl.pci_mc1 ||
3040 !pvt->pci_sad0 || !pvt->pci_sad1 ||
3041 !pvt->pci_ta) {
3046 if (!pvt->knl.pci_channel[i]) {
3053 if (!pvt->knl.pci_cha[i]) {
3080 struct sbridge_pvt *pvt = mci->pvt_info;
3103 if (pvt->info.type != SANDY_BRIDGE)
3151 if (pvt->info.type == KNIGHTS_LANDING) {
3200 pvt = mci->pvt_info;
3219 if (!pvt->is_lockstep && !pvt->is_cur_addr_mirrored && !pvt->is_close_pg)
3351 struct sbridge_pvt *pvt;
3364 sizeof(*pvt));
3372 pvt = mci->pvt_info;
3373 memset(pvt, 0, sizeof(*pvt));
3376 pvt->sbridge_dev = sbridge_dev;
3387 pvt->info.type = type;
3390 pvt->info.rankcfgr = IB_RANK_CFG_A;
3391 pvt->info.get_tolm = ibridge_get_tolm;
3392 pvt->info.get_tohm = ibridge_get_tohm;
3393 pvt->info.dram_rule = ibridge_dram_rule;
3394 pvt->info.get_memory_type = get_memory_type;
3395 pvt->info.get_node_id = get_node_id;
3396 pvt->info.get_ha = ibridge_get_ha;
3397 pvt->info.rir_limit = rir_limit;
3398 pvt->info.sad_limit = sad_limit;
3399 pvt->info.interleave_mode = interleave_mode;
3400 pvt->info.dram_attr = dram_attr;
3401 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3402 pvt->info.interleave_list = ibridge_interleave_list;
3403 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3404 pvt->info.get_width = ibridge_get_width;
3412 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3415 pvt->info.rankcfgr = SB_RANK_CFG_A;
3416 pvt->info.get_tolm = sbridge_get_tolm;
3417 pvt->info.get_tohm = sbridge_get_tohm;
3418 pvt->info.dram_rule = sbridge_dram_rule;
3419 pvt->info.get_memory_type = get_memory_type;
3420 pvt->info.get_node_id = get_node_id;
3421 pvt->info.get_ha = sbridge_get_ha;
3422 pvt->info.rir_limit = rir_limit;
3423 pvt->info.sad_limit = sad_limit;
3424 pvt->info.interleave_mode = interleave_mode;
3425 pvt->info.dram_attr = dram_attr;
3426 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
3427 pvt->info.interleave_list = sbridge_interleave_list;
3428 pvt->info.interleave_pkg = sbridge_interleave_pkg;
3429 pvt->info.get_width = sbridge_get_width;
3437 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3441 pvt->info.get_tolm = haswell_get_tolm;
3442 pvt->info.get_tohm = haswell_get_tohm;
3443 pvt->info.dram_rule = ibridge_dram_rule;
3444 pvt->info.get_memory_type = haswell_get_memory_type;
3445 pvt->info.get_node_id = haswell_get_node_id;
3446 pvt->info.get_ha = ibridge_get_ha;
3447 pvt->info.rir_limit = haswell_rir_limit;
3448 pvt->info.sad_limit = sad_limit;
3449 pvt->info.interleave_mode = interleave_mode;
3450 pvt->info.dram_attr = dram_attr;
3451 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3452 pvt->info.interleave_list = ibridge_interleave_list;
3453 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3454 pvt->info.get_width = ibridge_get_width;
3462 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3466 pvt->info.get_tolm = haswell_get_tolm;
3467 pvt->info.get_tohm = haswell_get_tohm;
3468 pvt->info.dram_rule = ibridge_dram_rule;
3469 pvt->info.get_memory_type = haswell_get_memory_type;
3470 pvt->info.get_node_id = haswell_get_node_id;
3471 pvt->info.get_ha = ibridge_get_ha;
3472 pvt->info.rir_limit = haswell_rir_limit;
3473 pvt->info.sad_limit = sad_limit;
3474 pvt->info.interleave_mode = interleave_mode;
3475 pvt->info.dram_attr = dram_attr;
3476 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3477 pvt->info.interleave_list = ibridge_interleave_list;
3478 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3479 pvt->info.get_width = broadwell_get_width;
3487 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3490 /* pvt->info.rankcfgr == ??? */
3491 pvt->info.get_tolm = knl_get_tolm;
3492 pvt->info.get_tohm = knl_get_tohm;
3493 pvt->info.dram_rule = knl_dram_rule;
3494 pvt->info.get_memory_type = knl_get_memory_type;
3495 pvt->info.get_node_id = knl_get_node_id;
3496 pvt->info.get_ha = knl_get_ha;
3497 pvt->info.rir_limit = NULL;
3498 pvt->info.sad_limit = knl_sad_limit;
3499 pvt->info.interleave_mode = knl_interleave_mode;
3500 pvt->info.dram_attr = dram_attr_knl;
3501 pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule);
3502 pvt->info.interleave_list = knl_interleave_list;
3503 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3504 pvt->info.get_width = knl_get_width;
3511 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);