Lines Matching defs:channel
287 #define MAX_DIMMS 3 /* Max DIMMS per channel */
394 struct sbridge_channel channel[NUM_CHANNELS];
514 * - 3 DDR3 channels, 2 DPC per channel
517 * - 4 DDR4 channels, 3 DPC per channel
520 * - 4 DDR4 channels, 3 DPC per channel
523 * - each IMC interfaces with a SMI 2 channel
524 * - each SMI channel interfaces with a scalable memory buffer
591 /* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */
631 * - 2 DDR3 channels, 2 DPC per channel
634 * - 4 DDR4 channels, 3 DPC per channel
637 * - 4 DDR4 channels, 3 DPC per channel
640 * - each IMC interfaces with a SMI 2 channel
641 * - each SMI channel interfaces with a scalable memory buffer
1022 * home agent bank (7, 8), or one of the per-channel memory
1210 /* Determine which memory controller is responsible for a given channel. */
1211 static int knl_channel_mc(int channel)
1213 WARN_ON(channel < 0 || channel >= 6);
1215 return channel < 3 ? 1 : 0;
1244 * entry 0: mc 0:2 channel 18:19
1245 * 1: mc 3:5 channel 20:21
1246 * 2: mc 6:8 channel 22:23
1247 * 3: mc 9:11 channel 24:25
1248 * 4: mc 12:14 channel 26:27
1249 * 5: mc 15:17 channel 28:29
1329 * interleaved, we know the individual contribution of each channel to
1332 * Finally, we have to check whether each channel participates in each SAD
1335 * Fortunately, KNL only supports one DIMM per channel, so once we know how
1336 * much memory the channel uses, we know the DIMM is at least that large.
1364 int channel;
1441 * We stop when we see the first channel again.
1531 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++)
1532 participants[channel] = 0;
1534 /* For each channel, does at least one CHA have
1535 * this channel mapped to the given target?
1537 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1544 mc_route_reg[cha]) == channel
1545 && !participants[channel]) {
1546 participants[channel] = 1;
1553 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1554 mc = knl_channel_mc(channel);
1555 if (participants[channel]) {
1556 edac_dbg(4, "mc channel %d contributes %lld bytes via sad entry %d\n",
1557 channel,
1560 mc_sizes[channel] +=
1645 pvt->channel[i].dimms++;
1662 edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
1672 pvt->channel[i].dimm[j].rowbits = order_base_2(rows);
1673 pvt->channel[i].dimm[j].colbits = order_base_2(cols);
1674 pvt->channel[i].dimm[j].bank_xor_enable =
1676 pvt->channel[i].dimm[j].amap_fine = GET_BITFIELD(amap, 0, 0);
1866 * Step 4) Get TAD offsets, per each channel
1869 if (!pvt->channel[i].dimms)
1886 * Step 6) Get RIR Wayness/Limit, per each channel
1889 if (!pvt->channel[i].dimms)
1988 amap_fine = pvt->channel[ch].dimm[dimmno].amap_fine;
1990 rowbits = pvt->channel[ch].dimm[dimmno].rowbits;
1991 colbits = pvt->channel[ch].dimm[dimmno].colbits;
1992 bank_xor_enable = pvt->channel[ch].dimm[dimmno].bank_xor_enable;
2195 * Step 2) Get memory channel
2203 sprintf(msg, "Can't discover the memory channel");
2211 sprintf(msg, "Can't discover the memory channel");
2275 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
2286 /* Calculate channel address */
2358 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
2373 u32 reg, channel = GET_BITFIELD(m->status, 0, 3);
2379 if (channel >= NUM_CHANNELS) {
2380 sprintf(msg, "Invalid channel 0x%x", channel);
2407 *channel_mask = 1 << channel;
2410 *channel_mask |= 1 << ((channel + 2) % 4);
2417 *channel_mask |= 1 << ((channel + 1) % 4);
2611 * channel like this
3047 sbridge_printk(KERN_ERR, "Missing channel %d\n", i);
3090 u32 channel = GET_BITFIELD(m->status, 0, 3);
3127 * cccc = channel
3152 if (channel == 14) {
3163 * Reported channel is in range 0-2, so we can't map it
3168 channel = knl_channel_remap(m->bank == 16, channel);
3169 channel_mask = 1 << channel;
3172 "%s%s err_code:%04x:%04x channel:%d (DIMM_%c)",
3176 mscod, errcode, channel, A + channel);
3179 channel, 0, -1,
3216 * EDAC core should be handling the channel mask, in order to point
3220 channel = first_channel;
3233 /* FIXME: need support for channel mask */
3235 if (channel == CHANNEL_UNSPECIFIED)
3236 channel = -1;
3241 channel, dimm, -1,