Lines Matching defs:drv

89 static int qcom_llcc_core_setup(struct llcc_drv_data *drv, struct regmap *llcc_bcast_regmap)
98 	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_2_enable,
104 	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->trp_interrupt_0_enable,
111 	ret = regmap_write(llcc_bcast_regmap, drv->edac_reg_offset->drp_ecc_error_cfg,
116 	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_2_enable,
122 	ret = regmap_write(llcc_bcast_regmap, drv->edac_reg_offset->drp_interrupt_enable,
129 qcom_llcc_clear_error_status(int err_type, struct llcc_drv_data *drv)
136 		ret = regmap_write(drv->bcast_regmap,
137 				   drv->edac_reg_offset->drp_interrupt_clear,
142 		ret = regmap_write(drv->bcast_regmap,
143 				   drv->edac_reg_offset->drp_ecc_error_cntr_clear,
150 		ret = regmap_write(drv->bcast_regmap,
151 				   drv->edac_reg_offset->trp_interrupt_0_clear,
156 		ret = regmap_write(drv->bcast_regmap,
157 				   drv->edac_reg_offset->trp_ecc_error_cntr_clear,
176 static void get_reg_offsets(struct llcc_drv_data *drv, int err_type,
179 	const struct llcc_edac_reg_offset *edac_reg_offset = drv->edac_reg_offset;
207 dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type)
214 	get_reg_offsets(drv, err_type, &regs);
218 		ret = regmap_read(drv->regmaps[bank], synd_reg,
227 	ret = regmap_read(drv->regmaps[bank], regs.count_status_reg,
237 	ret = regmap_read(drv->regmaps[bank], regs.ways_status_reg,
249 	return qcom_llcc_clear_error_status(err_type, drv);
255 	struct llcc_drv_data *drv = edev_ctl->dev->platform_data;
258 	ret = dump_syn_reg_values(drv, bank, err_type);
291 	struct llcc_drv_data *drv = edac_dev_ctl->dev->platform_data;
297 	for (i = 0; i < drv->num_banks; i++) {
298 		ret = regmap_read(drv->regmaps[i], drv->edac_reg_offset->drp_interrupt_status,
313 		ret = regmap_read(drv->regmaps[i], drv->edac_reg_offset->trp_interrupt_0_status,