Lines Matching defs:imc
157 struct igen6_imc imc[NUM_IMC];
344 struct igen6_imc *imc = &igen6_pvt->imc[mc];
351 mc_hash = readl(imc->window + MAD_MC_HASH_OFFSET);
513 struct igen6_imc *imc = &igen6_pvt->imc[res->mc];
524 hash = readl(imc->window + CHANNEL_HASH_OFFSET);
525 s_size = imc->ch_s_size;
526 l_map = imc->ch_l_map;
532 hash = readl(imc->window + CHANNEL_EHASH_OFFSET);
533 s_size = imc->dimm_s_size[idx];
534 l_map = imc->dimm_l_map[idx];
595 static u64 ecclog_read_and_clear(struct igen6_imc *imc)
597 u64 ecclog = readq(imc->window + ECC_ERROR_LOG_OFFSET);
601 writeq(ecclog, imc->window + ECC_ERROR_LOG_OFFSET);
608 static void errsts_clear(struct igen6_imc *imc)
612 if (pci_read_config_word(imc->pdev, ERRSTS_OFFSET, &errsts)) {
619 pci_write_config_word(imc->pdev, ERRSTS_OFFSET, errsts);
624 struct igen6_imc *imc = &igen6_pvt->imc[0];
628 rc = pci_read_config_word(imc->pdev, ERRCMD_OFFSET, &errcmd);
637 rc = pci_write_config_word(imc->pdev, ERRCMD_OFFSET, errcmd);
646 struct igen6_imc *imc;
651 imc = &igen6_pvt->imc[i];
655 ecclog = ecclog_read_and_clear(imc);
688 mci = igen6_pvt->imc[res.mc].mci;
706 errsts_clear(&igen6_pvt->imc[i]);
786 static bool igen6_check_ecc(struct igen6_imc *imc)
788 u32 activate = readl(imc->window + IBECC_ACTIVATE_OFFSET);
795 struct igen6_imc *imc = mci->pvt_info;
797 int i, j, ndimms, mc = imc->mc;
806 mad_inter = readl(imc->window + MAD_INTER_CHANNEL_OFFSET);
808 ecc = igen6_check_ecc(imc);
809 imc->ch_s_size = MAD_INTER_CHANNEL_CH_S_SIZE(mad_inter);
810 imc->ch_l_map = MAD_INTER_CHANNEL_CH_L_MAP(mad_inter);
813 mad_intra = readl(imc->window + MAD_INTRA_CH0_OFFSET + i * 4);
814 mad_dimm = readl(imc->window + MAD_DIMM_CH0_OFFSET + i * 4);
816 imc->dimm_l_size[i] = MAD_DIMM_CH_DIMM_L_SIZE(mad_dimm);
817 imc->dimm_s_size[i] = MAD_DIMM_CH_DIMM_S_SIZE(mad_dimm);
818 imc->dimm_l_map[i] = MAD_INTRA_CH_DIMM_L_MAP(mad_intra);
819 imc->size += imc->dimm_s_size[i];
820 imc->size += imc->dimm_l_size[i];
826 if (j ^ imc->dimm_l_map[i]) {
828 dsize = imc->dimm_s_size[i];
831 dsize = imc->dimm_l_size[i];
856 edac_dbg(0, "MC %d, total size %llu MiB\n", mc, imc->size >> 20);
866 static void igen6_reg_dump(struct igen6_imc *imc)
871 readl(imc->window + CHANNEL_HASH_OFFSET));
873 readl(imc->window + CHANNEL_EHASH_OFFSET));
875 readl(imc->window + MAD_INTER_CHANNEL_OFFSET));
877 readq(imc->window + ECC_ERROR_LOG_OFFSET));
881 readl(imc->window + MAD_INTRA_CH0_OFFSET + i * 4));
883 readl(imc->window + MAD_DIMM_CH0_OFFSET + i * 4));
931 static void igen6_reg_dump(struct igen6_imc *imc) {}
1007 struct igen6_imc *imc;
1044 mci->pvt_info = &igen6_pvt->imc[mc];
1046 imc = mci->pvt_info;
1047 device_initialize(&imc->dev);
1055 * for the first memory controller and assign a unique imc->dev
1058 mci->pdev = mc ? &imc->dev : &pdev->dev;
1059 imc->mc = mc;
1060 imc->pdev = pdev;
1061 imc->window = window;
1063 igen6_reg_dump(imc);
1075 imc->mci = mci;
1089 struct igen6_imc *imc;
1095 imc = &igen6_pvt->imc[i];
1096 mci = imc->mci;
1103 iounmap(imc->window);
1109 struct igen6_imc *imc = &igen6_pvt->imc[0];
1119 if (imc[0].size < imc[1].size) {
1120 ms_s_size = imc[0].size;
1123 ms_s_size = imc[1].size;