Lines Matching refs:pvt
439 struct i5400_pvt *pvt;
442 pvt = mci->pvt_info;
445 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
458 pci_read_config_dword(pvt->branchmap_werrors,
460 pci_read_config_word(pvt->branchmap_werrors,
462 pci_read_config_dword(pvt->branchmap_werrors,
466 pci_write_config_dword(pvt->branchmap_werrors,
476 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
484 pci_read_config_dword(pvt->branchmap_werrors,
486 pci_read_config_word(pvt->branchmap_werrors,
488 pci_read_config_dword(pvt->branchmap_werrors,
490 pci_read_config_dword(pvt->branchmap_werrors,
494 pci_write_config_dword(pvt->branchmap_werrors,
701 struct i5400_pvt *pvt;
703 pvt = mci->pvt_info;
706 pci_dev_put(pvt->branch_1);
707 pci_dev_put(pvt->branch_0);
708 pci_dev_put(pvt->fsb_error_regs);
709 pci_dev_put(pvt->branchmap_werrors);
720 struct i5400_pvt *pvt;
723 pvt = mci->pvt_info;
724 pvt->branchmap_werrors = NULL;
725 pvt->fsb_error_regs = NULL;
726 pvt->branch_0 = NULL;
727 pvt->branch_1 = NULL;
750 pvt->branchmap_werrors = pdev;
766 pci_dev_put(pvt->branchmap_werrors);
774 pvt->fsb_error_regs = pdev;
777 pci_name(pvt->system_address),
778 pvt->system_address->vendor, pvt->system_address->device);
780 pci_name(pvt->branchmap_werrors),
781 pvt->branchmap_werrors->vendor,
782 pvt->branchmap_werrors->device);
784 pci_name(pvt->fsb_error_regs),
785 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
787 pvt->branch_0 = pci_get_device(PCI_VENDOR_ID_INTEL,
789 if (!pvt->branch_0) {
795 pci_dev_put(pvt->fsb_error_regs);
796 pci_dev_put(pvt->branchmap_werrors);
803 if (pvt->maxch < CHANNELS_PER_BRANCH)
806 pvt->branch_1 = pci_get_device(PCI_VENDOR_ID_INTEL,
808 if (!pvt->branch_1) {
816 pci_dev_put(pvt->branch_0);
817 pci_dev_put(pvt->fsb_error_regs);
818 pci_dev_put(pvt->branchmap_werrors);
838 static int determine_amb_present_reg(struct i5400_pvt *pvt, int channel)
844 amb_present = pvt->b0_ambpresent1;
846 amb_present = pvt->b0_ambpresent0;
849 amb_present = pvt->b1_ambpresent1;
851 amb_present = pvt->b1_ambpresent0;
858 * determine_mtr(pvt, dimm, channel)
862 static int determine_mtr(struct i5400_pvt *pvt, int dimm, int channel)
879 mtr = pvt->b0_mtr[n];
881 mtr = pvt->b1_mtr[n];
919 static void handle_channel(struct i5400_pvt *pvt, int dimm, int channel,
926 mtr = determine_mtr(pvt, dimm, channel);
928 amb_present_reg = determine_amb_present_reg(pvt, channel);
957 static void calculate_dimm_size(struct i5400_pvt *pvt)
979 max_dimms = pvt->maxdimmperch;
997 for (channel = 0; channel < pvt->maxch; channel++) {
998 dinfo = &pvt->dimm_info[dimm][channel];
999 handle_channel(pvt, dimm, channel, dinfo);
1022 for (channel = 0; channel < pvt->maxch; channel++) {
1054 struct i5400_pvt *pvt;
1060 pvt = mci->pvt_info;
1062 pci_read_config_dword(pvt->system_address, AMBASE,
1063 &pvt->u.ambase_bottom);
1064 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
1065 &pvt->u.ambase_top);
1068 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
1071 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1072 pvt->tolm >>= 12;
1074 pvt->tolm, pvt->tolm);
1076 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
1078 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
1080 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
1081 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
1084 limit = (pvt->mir0 >> 4) & 0x0fff;
1085 way0 = pvt->mir0 & 0x1;
1086 way1 = pvt->mir0 & 0x2;
1089 limit = (pvt->mir1 >> 4) & 0xfff;
1090 way0 = pvt->mir1 & 0x1;
1091 way1 = pvt->mir1 & 0x2;
1100 pci_read_config_word(pvt->branch_0, where,
1101 &pvt->b0_mtr[slot_row]);
1104 slot_row, where, pvt->b0_mtr[slot_row]);
1106 if (pvt->maxch < CHANNELS_PER_BRANCH) {
1107 pvt->b1_mtr[slot_row] = 0;
1112 pci_read_config_word(pvt->branch_1, where,
1113 &pvt->b1_mtr[slot_row]);
1115 slot_row, where, pvt->b1_mtr[slot_row]);
1122 decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
1124 pci_read_config_word(pvt->branch_0, AMBPRESENT_0,
1125 &pvt->b0_ambpresent0);
1126 edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
1127 pci_read_config_word(pvt->branch_0, AMBPRESENT_1,
1128 &pvt->b0_ambpresent1);
1129 edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
1132 if (pvt->maxch < CHANNELS_PER_BRANCH) {
1133 pvt->b1_ambpresent0 = 0;
1134 pvt->b1_ambpresent1 = 0;
1139 decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
1141 pci_read_config_word(pvt->branch_1, AMBPRESENT_0,
1142 &pvt->b1_ambpresent0);
1144 pvt->b1_ambpresent0);
1145 pci_read_config_word(pvt->branch_1, AMBPRESENT_1,
1146 &pvt->b1_ambpresent1);
1148 pvt->b1_ambpresent1);
1153 calculate_dimm_size(pvt);
1167 struct i5400_pvt *pvt;
1174 pvt = mci->pvt_info;
1179 * FIXME: remove pvt->dimm_info[slot][channel] and use the 3
1185 mtr = determine_mtr(pvt, slot, channel);
1193 size_mb = pvt->dimm_info[slot][channel].megabytes;
1230 struct i5400_pvt *pvt;
1233 pvt = mci->pvt_info;
1236 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1242 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1256 struct i5400_pvt *pvt;
1284 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
1292 pvt = mci->pvt_info;
1293 pvt->system_address = pdev; /* Record this device in our private */
1294 pvt->maxch = MAX_CHANNELS;
1295 pvt->maxdimmperch = DIMMS_PER_CHANNEL;