Lines Matching defs:imc
102 static void __enable_retry_rd_err_log(struct skx_imc *imc, int chan, bool enable,
108 s = I10NM_GET_REG32(imc, chan, offsets_scrub[0]);
109 d = I10NM_GET_REG32(imc, chan, offsets_demand[0]);
111 d2 = I10NM_GET_REG32(imc, chan, offsets_demand2[0]);
115 imc->chan[chan].retry_rd_err_log_s = s;
116 imc->chan[chan].retry_rd_err_log_d = d;
118 imc->chan[chan].retry_rd_err_log_d2 = d2;
132 if (imc->chan[chan].retry_rd_err_log_s & RETRY_RD_ERR_LOG_UC)
134 if (imc->chan[chan].retry_rd_err_log_s & RETRY_RD_ERR_LOG_NOOVER)
136 if (!(imc->chan[chan].retry_rd_err_log_s & RETRY_RD_ERR_LOG_EN))
138 if (imc->chan[chan].retry_rd_err_log_d & RETRY_RD_ERR_LOG_UC)
140 if (imc->chan[chan].retry_rd_err_log_d & RETRY_RD_ERR_LOG_NOOVER)
142 if (!(imc->chan[chan].retry_rd_err_log_d & RETRY_RD_ERR_LOG_EN))
146 if (imc->chan[chan].retry_rd_err_log_d2 & RETRY_RD_ERR_LOG_UC)
148 if (!(imc->chan[chan].retry_rd_err_log_d2 & RETRY_RD_ERR_LOG_NOOVER))
150 if (!(imc->chan[chan].retry_rd_err_log_d2 & RETRY_RD_ERR_LOG_EN))
155 I10NM_SET_REG32(imc, chan, offsets_scrub[0], s);
156 I10NM_SET_REG32(imc, chan, offsets_demand[0], d);
158 I10NM_SET_REG32(imc, chan, offsets_demand2[0], d2);
164 struct skx_imc *imc;
174 imc = &d->imc[i];
175 if (!imc->mbase)
179 __enable_retry_rd_err_log(imc, j, enable,
189 imc = &d->imc[i];
190 if (!imc->mbase || !imc->hbm_mc)
194 __enable_retry_rd_err_log(imc, j, enable,
198 __enable_retry_rd_err_log(imc, j, enable,
210 struct skx_imc *imc = &res->dev->imc[res->imc];
220 if (!imc->mbase)
223 if (imc->hbm_mc) {
241 log0 = I10NM_GET_REG32(imc, res->channel, offsets[0]);
242 log1 = I10NM_GET_REG32(imc, res->channel, offsets[1]);
243 log3 = I10NM_GET_REG32(imc, res->channel, offsets[3]);
244 log4 = I10NM_GET_REG32(imc, res->channel, offsets[4]);
245 log5 = I10NM_GET_REG64(imc, res->channel, offsets[5]);
248 lxg0 = I10NM_GET_REG32(imc, res->channel, xffsets[0]);
249 lxg1 = I10NM_GET_REG32(imc, res->channel, xffsets[1]);
250 lxg3 = I10NM_GET_REG32(imc, res->channel, xffsets[3]);
251 lxg4 = I10NM_GET_REG32(imc, res->channel, xffsets[4]);
252 lxg5 = I10NM_GET_REG64(imc, res->channel, xffsets[5]);
256 log2a = I10NM_GET_REG64(imc, res->channel, offsets[2]);
262 lxg2a = I10NM_GET_REG64(imc, res->channel, xffsets[2]);
270 log2 = I10NM_GET_REG32(imc, res->channel, offsets[2]);
275 if (imc->hbm_mc) {
277 corr0 = I10NM_GET_REG32(imc, res->channel, 0x2c18);
278 corr1 = I10NM_GET_REG32(imc, res->channel, 0x2c1c);
279 corr2 = I10NM_GET_REG32(imc, res->channel, 0x2c20);
280 corr3 = I10NM_GET_REG32(imc, res->channel, 0x2c24);
282 corr0 = I10NM_GET_REG32(imc, res->channel, 0x2818);
283 corr1 = I10NM_GET_REG32(imc, res->channel, 0x281c);
284 corr2 = I10NM_GET_REG32(imc, res->channel, 0x2820);
285 corr3 = I10NM_GET_REG32(imc, res->channel, 0x2824);
288 corr0 = I10NM_GET_REG32(imc, res->channel, 0x22c18);
289 corr1 = I10NM_GET_REG32(imc, res->channel, 0x22c1c);
290 corr2 = I10NM_GET_REG32(imc, res->channel, 0x22c20);
291 corr3 = I10NM_GET_REG32(imc, res->channel, 0x22c24);
306 I10NM_SET_REG32(imc, res->channel, offsets[0], log0);
311 I10NM_SET_REG32(imc, res->channel, xffsets[0], lxg0);
523 if (d->imc[0].src_id == m->socketid) {
533 res->imc = bank / 4;
546 res->imc = bank / 2;
561 skx_printk(KERN_ERR, "No device for src_id %d imc %d\n",
562 m->socketid, res->imc);
662 * i10nm_imc_absent() - Check whether the memory controller @imc is absent
664 * @imc : The pointer to the structure of memory controller EDAC device.
668 static bool i10nm_imc_absent(struct skx_imc *imc)
676 mcmtr = I10NM_GET_MCMTR(imc, i);
749 d->imc[lmc].mbase = mbase;
750 if (i10nm_imc_absent(&d->imc[lmc])) {
753 d->imc[lmc].mbase = NULL;
757 d->imc[lmc].mdev = mdev;
822 d->imc[lmc].mdev = mdev;
830 pci_dev_put(d->imc[lmc].mdev);
831 d->imc[lmc].mdev = NULL;
838 d->imc[lmc].mbase = mbase;
839 d->imc[lmc].hbm_mc = true;
841 mcmtr = I10NM_GET_MCMTR(&d->imc[lmc], 0);
843 iounmap(d->imc[lmc].mbase);
844 d->imc[lmc].mbase = NULL;
845 d->imc[lmc].hbm_mc = false;
846 pci_dev_put(d->imc[lmc].mdev);
847 d->imc[lmc].mdev = NULL;
958 static bool i10nm_check_ecc(struct skx_imc *imc, int chan)
962 mcmtr = I10NM_GET_MCMTR(imc, chan);
972 struct skx_imc *imc = pvt->imc;
977 for (i = 0; i < imc->num_channels; i++) {
978 if (!imc->mbase)
982 amap = I10NM_GET_AMAP(imc, i);
985 mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i);
987 for (j = 0; j < imc->num_dimms; j++) {
989 mtr = I10NM_GET_DIMMMTR(imc, i, j);
991 mtr, mcddrtcfg, imc->mc, i, j);
995 imc, i, j, cfg);
997 ndimms += skx_get_nvdimm_info(dimm, imc, i, j,
1000 if (ndimms && !i10nm_check_ecc(imc, i)) {
1001 i10nm_printk(KERN_ERR, "ECC is disabled on imc %d channel %d\n",
1002 imc->mc, i);
1130 if (!d->imc[i].mdev)
1133 d->imc[i].mc = mc++;
1134 d->imc[i].lmc = i;
1135 d->imc[i].src_id = src_id;
1136 d->imc[i].node_id = node_id;
1137 if (d->imc[i].hbm_mc) {
1138 d->imc[i].chan_mmio_sz = cfg->hbm_chan_mmio_sz;
1139 d->imc[i].num_channels = cfg->hbm_chan_num;
1140 d->imc[i].num_dimms = cfg->hbm_dimm_num;
1142 d->imc[i].chan_mmio_sz = cfg->ddr_chan_mmio_sz;
1143 d->imc[i].num_channels = cfg->ddr_chan_num;
1144 d->imc[i].num_dimms = cfg->ddr_dimm_num;
1147 rc = skx_register_mci(&d->imc[i], d->imc[i].mdev,