Lines Matching defs:val32
27 static void edac_pci_read_dword(struct pci_dev *dev, int reg, u32 *val32)
31 ret = pci_read_config_dword(dev, reg, val32);
37 static void edac_pci_write_dword(struct pci_dev *dev, int reg, u32 val32)
41 ret = pci_write_config_dword(dev, reg, val32);
74 u32 val32;
78 edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
79 if (val32 & MEM_LIMIT_MASK)
80 edac_pci_write_dword(dev, REG_MEM_LIM, val32);
83 edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
84 if (val32 & INT_CTLR_DTS)
85 edac_pci_write_dword(dev, REG_INT_CTLR, val32);
88 edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
89 if (val32 & LNK_CTRL_CRCERR_A)
90 edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
93 edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
94 if (val32 & LNK_CTRL_CRCERR_B)
95 edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
103 edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
104 val32 |= INT_CTLR_PERR | INT_CTLR_SERR | INT_CTLR_DTSE;
105 edac_pci_write_dword(dev, REG_INT_CTLR, val32);
108 edac_pci_read_dword(dev, REG_STS_CMD, &val32);
109 val32 |= STS_CMD_SERREN;
110 edac_pci_write_dword(dev, REG_STS_CMD, val32);
113 edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
114 val32 |= LNK_CTRL_CRCFEN;
115 edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
118 edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
119 val32 |= LNK_CTRL_CRCFEN;
120 edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
125 u32 val32;
129 edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
130 val32 &= ~(INT_CTLR_PERR | INT_CTLR_SERR | INT_CTLR_DTSE);
131 edac_pci_write_dword(dev, REG_INT_CTLR, val32);
134 edac_pci_read_dword(dev, REG_STS_CMD, &val32);
135 val32 &= ~STS_CMD_SERREN;
136 edac_pci_write_dword(dev, REG_STS_CMD, val32);
139 edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
140 val32 &= ~LNK_CTRL_CRCFEN;
141 edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
144 edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
145 val32 &= ~LNK_CTRL_CRCFEN;
146 edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
153 u32 val32;
156 edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
157 if (val32 & MEM_LIMIT_MASK) {
162 val32 & MEM_LIMIT_DPE,
163 val32 & MEM_LIMIT_RSE,
164 val32 & MEM_LIMIT_RMA,
165 val32 & MEM_LIMIT_RTA,
166 val32 & MEM_LIMIT_STA,
167 val32 & MEM_LIMIT_MDPE);
169 val32 |= MEM_LIMIT_MASK;
170 edac_pci_write_dword(dev, REG_MEM_LIM, val32);
176 edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
177 if (val32 & INT_CTLR_DTS) {
180 printk(KERN_INFO "DTS: %d\n", val32 & INT_CTLR_DTS);
182 val32 |= INT_CTLR_DTS;
183 edac_pci_write_dword(dev, REG_INT_CTLR, val32);
189 edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
190 if (val32 & LNK_CTRL_CRCERR_A) {
193 printk(KERN_INFO "CRCERR: %d\n", val32 & LNK_CTRL_CRCERR_A);
195 val32 |= LNK_CTRL_CRCERR_A;
196 edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
202 edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
203 if (val32 & LNK_CTRL_CRCERR_B) {
206 printk(KERN_INFO "CRCERR: %d\n", val32 & LNK_CTRL_CRCERR_B);
208 val32 |= LNK_CTRL_CRCERR_B;
209 edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);