Lines Matching refs:pvt
135 #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
136 #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
137 #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
140 #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
141 #define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
142 #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
145 #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
166 #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
167 #define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
189 #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
190 #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
192 #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
194 #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
195 #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
219 #define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
220 #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
414 static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
416 u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
421 return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
424 static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
426 u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
431 return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
439 static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
441 if (pvt->fam == 0x15 && pvt->model >= 0x30)
442 return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
443 ((pvt->dct_sel_lo >> 6) & 0x3);
445 return ((pvt)->dct_sel_lo >> 6) & 0x3;
467 int (*dbam_to_cs)(struct amd64_pvt *pvt, u8 dct,
469 int (*hw_info_get)(struct amd64_pvt *pvt);
470 bool (*ecc_enabled)(struct amd64_pvt *pvt);
472 void (*dump_misc_regs)(struct amd64_pvt *pvt);
501 static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
503 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
505 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
508 return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
511 static inline u8 dhar_valid(struct amd64_pvt *pvt)
513 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
515 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
518 return (pvt)->dhar & BIT(0);
521 static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
523 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
525 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
528 return (pvt)->dct_sel_lo & 0xFFFFF800;