Lines Matching refs:value
40 * or higher value'.
184 * Scan the scrub rate mapping table for a close or matching bandwidth value to
185 * issue. If requested is too big, then use last maximum value found.
193 * map the configured rate (new_bw) to a value specific to the AMD64
287 /* The K8 treats this as a 40-bit value. However, bits 63-40 will be
319 * The value of this field should be the same for all DRAM Base
336 amd64_warn("DRAM Base[IntlvEn] junk value: 0x%x, BIOS bug?\n", intlv_en);
607 * store error injection section value which refers to one of 4 16-byte sections
618 unsigned long value;
621 ret = kstrtoul(data, 10, &value);
625 if (value > 3) {
626 amd64_warn("%s: invalid section 0x%lx\n", __func__, value);
630 pvt->injection.section = (u32) value;
643 * store error injection word value which refers to one of 9 16-bit word of the
654 unsigned long value;
657 ret = kstrtoul(data, 10, &value);
661 if (value > 8) {
662 amd64_warn("%s: invalid word 0x%lx\n", __func__, value);
666 pvt->injection.word = (u32) value;
690 unsigned long value;
693 ret = kstrtoul(data, 16, &value);
697 if (value & 0xFFFF0000) {
698 amd64_warn("%s: invalid EccVector: 0x%lx\n", __func__, value);
702 pvt->injection.bit_map = (u32) value;
716 unsigned long value;
720 ret = kstrtoul(data, 10, &value);
724 /* Form value to choose 16-byte section of cacheline */
750 unsigned long value;
753 ret = kstrtoul(data, 10, &value);
757 /* Form value to choose 16-byte section of cacheline */
847 * hole. If not, skip to step 3 below. Else get the value of the
849 * offset defined by this value from the SysAddr.
880 * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8
895 * @intlv_en is the value of the IntlvEn field from a DRAM Base register
984 * system and what the lowest AMD Node ID value is for the GPU nodes. Use this
985 * info to fixup the Linux logical "Node ID" value set in the AMD NB code and EDAC.
1403 * calculation. We pass dimm value to the dbam_to_cs
1433 * value of '0' here to get dcsm value.
1872 * We use a Chip Select value of '0' to obtain dcsm.
1874 * 'Rank' value on a DCT. But this is not the common case. So,
2143 * Basically, it calculates a value with which to shift the
3114 * F1 (AddrMap) and F2 (Dct) devices. Return negative value on error.
3521 u32 value, mask = 0x3; /* UECC/CECC enable */
3528 amd64_read_pci_cfg(F3, NBCTL, &value);
3530 s->old_nbctl = value & mask;
3533 value |= mask;
3534 amd64_write_pci_cfg(F3, NBCTL, value);
3536 amd64_read_pci_cfg(F3, NBCFG, &value);
3539 nid, value, !!(value & NBCFG_ECC_ENABLE));
3541 if (!(value & NBCFG_ECC_ENABLE)) {
3547 value |= NBCFG_ECC_ENABLE;
3548 amd64_write_pci_cfg(F3, NBCFG, value);
3550 amd64_read_pci_cfg(F3, NBCFG, &value);
3552 if (!(value & NBCFG_ECC_ENABLE)) {
3564 nid, value, !!(value & NBCFG_ECC_ENABLE));
3572 u32 value, mask = 0x3; /* UECC/CECC enable */
3577 amd64_read_pci_cfg(F3, NBCTL, &value);
3578 value &= ~mask;
3579 value |= s->old_nbctl;
3581 amd64_write_pci_cfg(F3, NBCTL, value);
3585 amd64_read_pci_cfg(F3, NBCFG, &value);
3586 value &= ~NBCFG_ECC_ENABLE;
3587 amd64_write_pci_cfg(F3, NBCFG, value);
3600 u32 value;
3602 amd64_read_pci_cfg(pvt->F3, NBCFG, &value);
3604 ecc_en = !!(value & NBCFG_ECC_ENABLE);