Lines Matching refs:range
353 "range for node %d with node interleaving enabled.\n",
610 * range: 0..3
646 * range: 0..8
840 * Limit registers for node n. If the SysAddr is not within the range
846 * the range of relocated addresses (starting at 0x100000000) from the DRAM
1156 /* Check if address range is valid. */
1158 pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n",
1989 static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
1994 int off = range << 3;
1997 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo);
1998 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo);
2003 if (!dram_rw(pvt, range))
2006 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi);
2007 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi);
2013 nb = node_to_amd_nb(dram_dst_node(pvt, range));
2030 pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0);
2033 pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16;
2035 pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0);
2038 pvt->ranges[range].lim.hi |= llim >> 13;
2292 edac_dbg(0, "F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",
2299 edac_dbg(0, " Address range split per DCT: %s\n",
2394 static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range,
2399 u64 dram_base = get_dram_base(pvt, range);
2406 * base address of high range is below 4Gb
2413 * remove high range offset from sys_addr
2549 static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
2558 u8 node_id = dram_dst_node(pvt, range);
2559 u8 intlv_en = dram_intlv_en(pvt, range);
2560 u32 intlv_sel = dram_intlv_sel(pvt, range);
2562 edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
2563 range, sys_addr, get_dram_limit(pvt, range));
2591 chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr,
2629 static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
2641 u8 node_id = dram_dst_node(pvt, range);
2642 u8 intlv_en = dram_intlv_en(pvt, range);
2650 edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
2651 range, sys_addr, get_dram_limit(pvt, range));
2653 if (!(get_dram_base(pvt, range) <= sys_addr) &&
2654 !(get_dram_limit(pvt, range) >= sys_addr))
2756 unsigned range;
2758 for (range = 0; range < DRAM_RANGES; range++) {
2759 if (!dram_rw(pvt, range))
2763 cs_found = f15_m30h_match_to_this_node(pvt, range,
2767 else if ((get_dram_base(pvt, range) <= sys_addr) &&
2768 (get_dram_limit(pvt, range) >= sys_addr)) {
2769 cs_found = f1x_match_to_this_node(pvt, range,
3193 unsigned int range;
3216 for (range = 0; range < DRAM_RANGES; range++) {
3219 /* read settings for this DRAM range */
3220 read_dram_base_limit_regs(pvt, range);
3222 rw = dram_rw(pvt, range);
3226 edac_dbg(1, " DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n",
3227 range,
3228 get_dram_base(pvt, range),
3229 get_dram_limit(pvt, range));
3232 dram_intlv_en(pvt, range) ? "Enabled" : "Disabled",
3235 dram_intlv_sel(pvt, range),
3236 dram_dst_node(pvt, range));
3273 * Values range from: 0 to 15