Lines Matching refs:edac_dbg
362 edac_dbg(2, "sys_addr 0x%lx doesn't match any node\n",
461 edac_dbg(2, "InputAddr 0x%lx matches csrow %d (node %d)\n",
468 edac_dbg(2, "no matching csrow for InputAddr 0x%lx (MC node %d)\n",
497 edac_dbg(1, " revision %d for node %d does not support DHAR\n",
504 edac_dbg(1, " Dram Memory Hoisting is DISABLED on this system\n");
509 edac_dbg(1, " Dram Memory Hoisting is DISABLED on this node %d\n",
538 edac_dbg(1, " DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",
734 edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);
783 edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);
870 edac_dbg(2, "using DHAR to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
889 edac_dbg(2, "using DRAM Base register to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
926 edac_dbg(2, " Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",
944 edac_dbg(2, "SysAddr 0x%lx translates to InputAddr 0x%lx\n",
1392 edac_dbg(1, "F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",
1426 edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr);
1435 edac_dbg(1, " LRDIMM %dx rank multiply\n", (dcsm & 0x3));
1438 edac_dbg(1, "All DIMMs support ECC:%s\n",
1442 edac_dbg(1, " PAR/ERR parity: %s\n",
1446 edac_dbg(1, " DCT 128bit mode width: %s\n",
1449 edac_dbg(1, " x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",
1490 edac_dbg(1, "3R interleaving in use.\n");
1522 edac_dbg(1, "CS%d DIMM%d AddrMasks:\n", csrow_nr, dimm);
1523 edac_dbg(1, " Original AddrMask: 0x%x\n", addr_mask_orig);
1524 edac_dbg(1, " Deinterleaved AddrMask: 0x%x\n", addr_mask_deinterleaved);
1614 edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg);
1615 edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg);
1616 edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);
1617 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);
1620 edac_dbg(1, "UMC%d ECC bad symbol: 0x%x\n", i, tmp);
1623 edac_dbg(1, "UMC%d UMC cap: 0x%x\n", i, tmp);
1624 edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi);
1626 edac_dbg(1, "UMC%d ECC capable: %s, ChipKill ECC capable: %s\n",
1629 edac_dbg(1, "UMC%d All DIMMs support ECC: %s\n",
1631 edac_dbg(1, "UMC%d x4 DIMMs present: %s\n",
1633 edac_dbg(1, "UMC%d x16 DIMMs present: %s\n",
1640 edac_dbg(1, "UMC%d LRDIMM %dx rank multiply\n",
1650 edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);
1652 edac_dbg(1, " NB two channel DRAM capable: %s\n",
1655 edac_dbg(1, " ECC capable: %s, ChipKill ECC capable: %s\n",
1661 edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);
1663 edac_dbg(1, "F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, offset: 0x%08x\n",
1680 edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
1734 edac_dbg(0, " DCSB%d[%d]=0x%08x reg: 0x%x\n",
1738 edac_dbg(0, " DCSB_SEC%d[%d]=0x%08x reg: 0x%x\n",
1753 edac_dbg(0, " DCSM%d[%d]=0x%08x reg: 0x%x\n",
1757 edac_dbg(0, " DCSM_SEC%d[%d]=0x%08x reg: 0x%x\n",
1777 edac_dbg(0, " DCSB0[%d]=0x%08x reg: F2x%x\n",
1784 edac_dbg(0, " DCSB1[%d]=0x%08x reg: F2x%x\n",
1796 edac_dbg(0, " DCSM0[%d]=0x%08x reg: F2x%x\n",
1803 edac_dbg(0, " DCSM1[%d]=0x%08x reg: F2x%x\n",
1842 edac_dbg(1, " UMC%d DIMM type: %s\n", i, edac_mem_types[umc->dram_type]);
1900 edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]);
2292 edac_dbg(0, "F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",
2295 edac_dbg(0, " DCTs operate in %s mode\n",
2299 edac_dbg(0, " Address range split per DCT: %s\n",
2302 edac_dbg(0, " data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n",
2306 edac_dbg(0, " channel interleave: %s, "
2484 edac_dbg(1, "input addr: 0x%llx, DCT: %d\n", in_addr, dct);
2492 edac_dbg(1, " CSROW=%d CSBase=0x%llx CSMask=0x%llx\n",
2497 edac_dbg(1, " (InputAddr & ~CSMask)=0x%llx (CSBase & ~CSMask)=0x%llx\n",
2507 edac_dbg(1, " MATCH csrow=%d\n", cs_found);
2562 edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
2619 edac_dbg(1, " Normalized DCT addr: 0x%llx\n", chan_addr);
2650 edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
2731 edac_dbg(1, " Normalized DCT addr: 0x%llx\n", chan_addr);
2907 edac_dbg(0, "syndrome(%x) not found\n", syndrome);
3122 edac_dbg(1, "F1 not found: device 0x%x\n", pci_id1);
3132 edac_dbg(1, "F2 not found: device 0x%x\n", pci_id2);
3139 edac_dbg(1, "F1: %s\n", pci_name(pvt->F1));
3140 edac_dbg(1, "F2: %s\n", pci_name(pvt->F2));
3141 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
3201 edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem);
3207 edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2);
3209 edac_dbg(0, " TOP_MEM2 disabled\n");
3226 edac_dbg(1, " DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n",
3231 edac_dbg(1, " IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n",
3300 edac_dbg(0, "csrow: %d, channel: %d, DBAM idx: %d\n",
3302 edac_dbg(0, "nr_pages/channel: %u\n", nr_pages);
3317 edac_dbg(0, "csrow: %d, channel: %d, cs_mode %d\n",
3319 edac_dbg(0, "nr_pages/channel: %u\n", nr_pages);
3352 edac_dbg(1, "MC node: %d, csrow: %d\n",
3382 edac_dbg(0, "node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",
3401 edac_dbg(1, "MC node: %d, csrow: %d\n",
3417 edac_dbg(1, "Total csrow%d pages: %u\n", i, nr_pages);
3465 edac_dbg(0, "core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
3538 edac_dbg(0, "1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
3563 edac_dbg(0, "2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
3608 edac_dbg(0, "NB MCE bank disabled, set MSR 0x%08x[4] on node %d to enable.\n",
3611 edac_dbg(3, "Node %d: DRAM ECC %s.\n", nid, (ecc_en ? "enabled" : "disabled"));
3643 edac_dbg(0, "Node %d: No enabled UMCs.\n", nid);
3645 edac_dbg(3, "Node %d: DRAM ECC %s.\n", nid, (ecc_en ? "enabled" : "disabled"));
3813 edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg);
3814 edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);
3815 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);
3816 edac_dbg(1, "UMC%d All HBMs support ECC: yes\n", i);
3830 edac_dbg(0, "csrow: %d, channel: %d\n", csrow_nr, dct);
3831 edac_dbg(0, "nr_pages/channel: %u\n", nr_pages);
3849 edac_dbg(1, "MC node: %d, csrow: %d\n",
3934 edac_dbg(0, " DCSB%d[%d]=0x%08x reg: 0x%x\n",
3942 edac_dbg(0, " DCSM%d[%d]=0x%08x reg: 0x%x\n",
4213 edac_dbg(1, "failed edac_mc_add_mc()\n");