Lines Matching refs:csrow_nr
1498 int csrow_nr, int dimm)
1522 edac_dbg(1, "CS%d DIMM%d AddrMasks:\n", csrow_nr, dimm);
1534 unsigned int cs_mode, int csrow_nr)
1536 int cs_mask_nr = csrow_nr;
1545 if (!(cs_mode & CS_EVEN) && !(csrow_nr & 1))
1549 if (!(cs_mode & CS_ODD) && (csrow_nr & 1))
1570 dimm = csrow_nr >> 1;
1576 if ((csrow_nr & 1) && (cs_mode & CS_ODD_SECONDARY))
1581 return __addr_mask_to_cs_size(addr_mask_orig, cs_mode, csrow_nr, dimm);
3259 * @csrow_nr ChipSelect Row Number (0..NUM_CHIPSELECTS-1)
3289 static u32 dct_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
3294 csrow_nr >>= 1;
3295 cs_mode = DBAM_DIMM(csrow_nr, dbam);
3297 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr);
3301 csrow_nr, dct, cs_mode);
3309 int csrow_nr = csrow_nr_orig;
3312 cs_mode = umc_get_cs_mode(csrow_nr >> 1, dct, pvt);
3314 nr_pages = umc_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr);
3784 unsigned int cs_mode, int csrow_nr)
3786 u32 addr_mask_orig = pvt->csels[umc].csmasks[csrow_nr];
3788 return __addr_mask_to_cs_size(addr_mask_orig, cs_mode, csrow_nr, csrow_nr >> 1);
3822 static u32 gpu_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
3827 nr_pages = gpu_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr);
3830 edac_dbg(0, "csrow: %d, channel: %d\n", csrow_nr, dct);