Lines Matching refs:cs_mode
1468 int cs_mode = 0;
1471 cs_mode |= CS_EVEN_PRIMARY;
1474 cs_mode |= CS_ODD_PRIMARY;
1478 cs_mode |= CS_ODD_SECONDARY;
1491 cs_mode |= CS_3R_INTERLEAVE;
1494 return cs_mode;
1497 static int __addr_mask_to_cs_size(u32 addr_mask_orig, unsigned int cs_mode,
1517 num_zero_bits = msb - weight - !!(cs_mode & CS_3R_INTERLEAVE);
1534 unsigned int cs_mode, int csrow_nr)
1541 if (!cs_mode)
1545 if (!(cs_mode & CS_EVEN) && !(csrow_nr & 1))
1549 if (!(cs_mode & CS_ODD) && (csrow_nr & 1))
1576 if ((csrow_nr & 1) && (cs_mode & CS_ODD_SECONDARY))
1581 return __addr_mask_to_cs_size(addr_mask_orig, cs_mode, csrow_nr, dimm);
1586 int dimm, size0, size1, cs0, cs1, cs_mode;
1594 cs_mode = umc_get_cs_mode(dimm, ctrl, pvt);
1596 size0 = umc_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs0);
1597 size1 = umc_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs1);
2112 unsigned cs_mode, int cs_mask_nr)
2117 WARN_ON(cs_mode > 11);
2118 return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
2122 WARN_ON(cs_mode > 10);
2126 * contest, maps cs_mode values to DIMM chip select sizes. The
2129 * cs_mode CS size (mb)
2148 diff = cs_mode/3 + (unsigned)(cs_mode > 5);
2150 return 32 << (cs_mode - diff);
2153 WARN_ON(cs_mode > 6);
2154 return 32 << cs_mode;
2216 unsigned cs_mode, int cs_mask_nr)
2220 WARN_ON(cs_mode > 11);
2223 return ddr3_cs_size(cs_mode, dclr & WIDTH_128);
2225 return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
2232 unsigned cs_mode, int cs_mask_nr)
2234 WARN_ON(cs_mode > 12);
2236 return ddr3_cs_size(cs_mode, false);
2241 unsigned cs_mode, int cs_mask_nr)
2246 WARN_ON(cs_mode > 12);
2249 if (cs_mode > 9)
2252 cs_size = ddr4_cs_size(cs_mode);
2258 cs_size = ddr3_lrdimm_cs_size(cs_mode, rank_multiply);
2261 if (cs_mode == 0x1)
2264 cs_size = ddr3_cs_size(cs_mode, false);
2274 unsigned cs_mode, int cs_mask_nr)
2276 WARN_ON(cs_mode > 12);
2278 if (cs_mode == 6 || cs_mode == 8 ||
2279 cs_mode == 9 || cs_mode == 12)
2282 return ddr3_cs_size(cs_mode, false);
3292 u32 cs_mode, nr_pages;
3295 cs_mode = DBAM_DIMM(csrow_nr, dbam);
3297 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr);
3301 csrow_nr, dct, cs_mode);
3310 u32 cs_mode, nr_pages;
3312 cs_mode = umc_get_cs_mode(csrow_nr >> 1, dct, pvt);
3314 nr_pages = umc_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr);
3317 edac_dbg(0, "csrow: %d, channel: %d, cs_mode %d\n",
3318 csrow_nr_orig, dct, cs_mode);
3784 unsigned int cs_mode, int csrow_nr)
3788 return __addr_mask_to_cs_size(addr_mask_orig, cs_mode, csrow_nr, csrow_nr >> 1);
3793 int size, cs_mode, cs = 0;
3797 cs_mode = CS_EVEN_PRIMARY | CS_ODD_PRIMARY;
3800 size = gpu_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs);
3825 int cs_mode = CS_EVEN_PRIMARY | CS_ODD_PRIMARY;
3827 nr_pages = gpu_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr);