Lines Matching refs:DHAR
487 * complete 32-bit values despite the fact that the bitfields in the DHAR
497 edac_dbg(1, " revision %d for node %d does not support DHAR\n",
528 * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the
538 edac_dbg(1, " DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",
832 * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled,
834 * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting.
844 * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is
848 * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the
867 /* use DHAR to translate SysAddr to DramAddr */
870 edac_dbg(2, "using DHAR to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
3239 amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar);