Lines Matching defs:sys_addr
280 * returns true if the SysAddr given by sys_addr matches the
283 static bool base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, u8 nid)
293 addr = sys_addr & 0x000000ffffffffffull;
306 u64 sys_addr)
327 if (base_limit_match(pvt, sys_addr, node_id))
340 bits = (((u32) sys_addr) >> 12) & intlv_en;
350 /* sanity test for sys_addr */
351 if (unlikely(!base_limit_match(pvt, sys_addr, node_id))) {
352 amd64_warn("%s: sys_addr 0x%llx falls outside base/limit address"
354 __func__, sys_addr, node_id);
362 edac_dbg(2, "sys_addr 0x%lx doesn't match any node\n",
363 (unsigned long)sys_addr);
827 * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is
828 * assumed that sys_addr maps to the node given by mci.
855 static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr)
865 if ((sys_addr >= (1ULL << 32)) &&
866 (sys_addr < ((1ULL << 32) + hole_size))) {
868 dram_addr = sys_addr - hole_offset;
871 (unsigned long)sys_addr,
880 * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8
882 * sys_addr below. If bit 39 of sys_addr is 1 then the bits we
887 dram_addr = (sys_addr & GENMASK_ULL(39, 0)) - dram_base;
890 (unsigned long)sys_addr, (unsigned long)dram_addr);
934 * Translate the SysAddr represented by @sys_addr to an InputAddr. It is
935 * assumed that @sys_addr maps to the node given by mci.
937 static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr)
942 dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr));
945 (unsigned long)sys_addr, (unsigned long)input_addr);
959 * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address
963 * the error). Return the number of the csrow that sys_addr maps to, or -1 on
966 static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr)
970 csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr));
974 "address 0x%lx\n", (unsigned long)sys_addr);
1116 static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
1314 *sys_addr = ctx.ret_addr;
2043 static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
2048 error_address_to_page_and_offset(sys_addr, err);
2054 err->src_mci = find_mc_by_sys_addr(mci, sys_addr);
2057 (unsigned long)sys_addr);
2062 /* Now map the sys_addr to a CSROW */
2063 err->csrow = sys_addr_to_csrow(err->src_mci, sys_addr);
2093 err->channel = ((sys_addr & BIT(3)) != 0);
2319 static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
2330 select = (sys_addr >> 8) & 0x3;
2336 channel = (sys_addr >> 8) & 0x3;
2339 channel = (sys_addr >> 9) & 0x3;
2350 static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
2369 return sys_addr >> 6 & 1;
2373 u32 temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) & 1;
2375 return ((sys_addr >> shift) & 1) ^ temp;
2381 return (sys_addr >> shift) & 1;
2384 return (sys_addr >> (12 + hweight8(intlv_en))) & 1;
2393 /* Convert the sys_addr to the normalized DCT address */
2395 u64 sys_addr, bool hi_rng,
2409 * sys_addr > 4Gb
2411 * remove hole offset from sys_addr
2413 * remove high range offset from sys_addr
2418 (sys_addr >= BIT_64(32)))
2426 * sys_addr > 4Gb
2432 if (dhar_valid(pvt) && (sys_addr >= BIT_64(32)))
2438 return (sys_addr & GENMASK_ULL(47,6)) - (chan_off & GENMASK_ULL(47,23));
2519 static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr)
2526 return sys_addr;
2532 return sys_addr;
2537 tmp_addr = sys_addr >> 27;
2539 if (!(sys_addr >> 34) &&
2543 return sys_addr ^ (u64)swap_base << 27;
2545 return sys_addr;
2548 /* For a given @dram_range, check if @sys_addr falls within it. */
2550 u64 sys_addr, int *chan_sel)
2563 range, sys_addr, get_dram_limit(pvt, range));
2566 dhar_base(pvt) <= sys_addr &&
2567 sys_addr < BIT_64(32)) {
2569 sys_addr);
2573 if (intlv_en && (intlv_sel != ((sys_addr >> 12) & intlv_en)))
2576 sys_addr = f1x_swap_interleaved_region(pvt, sys_addr);
2586 ((sys_addr >> 27) >= (dct_sel_base >> 11)))
2589 channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en);
2591 chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr,
2630 u64 sys_addr, int *chan_sel)
2651 range, sys_addr, get_dram_limit(pvt, range));
2653 if (!(get_dram_base(pvt, range) <= sys_addr) &&
2654 !(get_dram_limit(pvt, range) >= sys_addr))
2658 dhar_base(pvt) <= sys_addr &&
2659 sys_addr < BIT_64(32)) {
2661 sys_addr);
2665 /* Verify sys_addr is within DCT Range. */
2670 !(dct_base <= (sys_addr >> 27) &&
2671 dct_limit >= (sys_addr >> 27)))
2681 channel = f1x_determine_channel(pvt, sys_addr, false, intlv_en);
2683 channel = f15_m30h_determine_channel(pvt, sys_addr, intlv_en,
2693 if (leg_mmio_hole && (sys_addr >= BIT_64(32)))
2698 chan_addr = sys_addr - chan_offset;
2752 u64 sys_addr,
2764 sys_addr,
2767 else if ((get_dram_base(pvt, range) <= sys_addr) &&
2768 (get_dram_limit(pvt, range) >= sys_addr)) {
2770 sys_addr, chan_sel);
2780 * a @sys_addr to NodeID, DCT (channel) and chip select (CSROW).
2782 * The @sys_addr is usually an error address received from the hardware
2785 static void f1x_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
2790 error_address_to_page_and_offset(sys_addr, err);
2792 err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel);
3017 u64 sys_addr;
3036 sys_addr = get_error_address(pvt, m);
3041 pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err);
3070 u64 sys_addr;
3101 if (umc_normaddr_to_sysaddr(m->addr, pvt->mc_node_id, err.channel, &sys_addr)) {
3106 error_address_to_page_and_offset(sys_addr, &err);