Lines Matching defs:ctrl
1368 static void dct_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
1370 u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases;
1371 u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0;
1379 WARN_ON(ctrl != 0);
1383 dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1
1385 dcsb = (ctrl && !dct_ganging_enabled(pvt)) ?
1388 } else if (ctrl) {
1393 ctrl, dbam);
1395 edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl);
1407 size0 = pvt->ops->dbam_to_cs(pvt, ctrl,
1413 size1 = pvt->ops->dbam_to_cs(pvt, ctrl,
1465 static int umc_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt)
1470 if (csrow_enabled(2 * dimm, ctrl, pvt))
1473 if (csrow_enabled(2 * dimm + 1, ctrl, pvt))
1477 if (csrow_sec_enabled(2 * dimm + 1, ctrl, pvt))
1485 for_each_chip_select(base, ctrl, pvt)
1486 count += csrow_enabled(base, ctrl, pvt);
1489 pvt->csels[ctrl].csmasks[0] == pvt->csels[ctrl].csmasks[1]) {
1584 static void umc_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
1588 edac_printk(KERN_DEBUG, EDAC_MC, "UMC%d chip selects:\n", ctrl);
1594 cs_mode = umc_get_cs_mode(dimm, ctrl, pvt);
1596 size0 = umc_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs0);
1597 size1 = umc_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs1);
1616 edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);
1617 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);
3791 static void gpu_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
3795 edac_printk(KERN_DEBUG, EDAC_MC, "UMC%d chip selects:\n", ctrl);
3799 for_each_chip_select(cs, ctrl, pvt) {
3800 size = gpu_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs);
3814 edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);
3815 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);