Lines Matching refs:reg
211 * @reg: register base address
227 void __iomem *reg;
253 * @reg: register base address
262 void __iomem *reg;
742 u32 reg;
744 reg = (XILINX_DPDMA_INTR_CHAN_MASK << chan->id)
746 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, reg);
747 reg = (XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id)
749 dpdma_write(chan->xdev->reg, XILINX_DPDMA_EIEN, reg);
751 reg = XILINX_DPDMA_CH_CNTL_ENABLE
758 dpdma_set(chan->reg, XILINX_DPDMA_CH_CNTL, reg);
769 u32 reg;
771 reg = XILINX_DPDMA_INTR_CHAN_MASK << chan->id;
772 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, reg);
773 reg = XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id;
774 dpdma_write(chan->xdev->reg, XILINX_DPDMA_EIEN, reg);
776 dpdma_clr(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_ENABLE);
787 dpdma_set(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_PAUSE);
798 dpdma_clr(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_PAUSE);
831 u32 reg, channels;
864 dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR,
867 dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE,
887 reg = XILINX_DPDMA_GBL_TRIG_MASK(channels);
889 reg = XILINX_DPDMA_GBL_RETRIG_MASK(channels);
891 dpdma_write(xdev->reg, XILINX_DPDMA_GBL, reg);
905 dpdma_read(chan->reg, XILINX_DPDMA_CH_STATUS));
935 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IDS,
961 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN,
996 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN,
1083 desc_id = dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_ID)
1152 dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE),
1153 dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR));
1156 dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDRE),
1157 dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDR));
1439 dpdma_write(xdev->reg, XILINX_DPDMA_IDS,
1441 dpdma_write(xdev->reg, XILINX_DPDMA_EIDS,
1457 dpdma_write(xdev->reg, XILINX_DPDMA_IEN, XILINX_DPDMA_INTR_ALL);
1458 dpdma_write(xdev->reg, XILINX_DPDMA_EIEN, XILINX_DPDMA_EINTR_ALL);
1469 dpdma_write(xdev->reg, XILINX_DPDMA_IDS, XILINX_DPDMA_INTR_ALL);
1470 dpdma_write(xdev->reg, XILINX_DPDMA_EIDS, XILINX_DPDMA_EINTR_ALL);
1492 dpdma_write(xdev->reg, XILINX_DPDMA_IEN,
1494 dpdma_write(xdev->reg, XILINX_DPDMA_EIEN,
1510 status = dpdma_read(xdev->reg, XILINX_DPDMA_ISR);
1511 error = dpdma_read(xdev->reg, XILINX_DPDMA_EISR);
1515 dpdma_write(xdev->reg, XILINX_DPDMA_ISR, status);
1516 dpdma_write(xdev->reg, XILINX_DPDMA_EISR, error);
1564 chan->reg = xdev->reg + XILINX_DPDMA_CH_BASE
1609 void __iomem *reg;
1616 reg = xdev->reg + XILINX_DPDMA_CH_BASE
1618 dpdma_clr(reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_ENABLE);
1622 dpdma_write(xdev->reg, XILINX_DPDMA_ISR, XILINX_DPDMA_INTR_ALL);
1623 dpdma_write(xdev->reg, XILINX_DPDMA_EISR, XILINX_DPDMA_EINTR_ALL);
1648 xdev->reg = devm_platform_ioremap_resource(pdev, 0);
1649 if (IS_ERR(xdev->reg))
1650 return PTR_ERR(xdev->reg);