Lines Matching defs:sw_desc
494 * @sw_desc: The software descriptor in which to set DMA addresses
501 * descriptor DMA address is set to the DMA address of @sw_desc. @prev may be
502 * identical to @sw_desc for cyclic transfers.
505 struct xilinx_dpdma_sw_desc *sw_desc,
510 struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;
537 prev->hw.next_desc = lower_32_bits(sw_desc->dma_addr);
541 upper_32_bits(sw_desc->dma_addr));
555 struct xilinx_dpdma_sw_desc *sw_desc;
558 sw_desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &dma_addr);
559 if (!sw_desc)
562 sw_desc->dma_addr = dma_addr;
564 return sw_desc;
570 * @sw_desc: software descriptor to free
576 struct xilinx_dpdma_sw_desc *sw_desc)
578 dma_pool_free(chan->desc_pool, sw_desc, sw_desc->dma_addr);
591 struct xilinx_dpdma_sw_desc *sw_desc;
598 list_for_each_entry(sw_desc, &tx_desc->descriptors, node) {
599 struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;
602 dev_dbg(dev, "descriptor DMA addr: %pad\n", &sw_desc->dma_addr);
656 struct xilinx_dpdma_sw_desc *sw_desc, *next;
664 list_for_each_entry_safe(sw_desc, next, &desc->descriptors, node) {
665 list_del(&sw_desc->node);
666 xilinx_dpdma_chan_free_sw_desc(desc->chan, sw_desc);
688 struct xilinx_dpdma_sw_desc *sw_desc;
704 sw_desc = xilinx_dpdma_chan_alloc_sw_desc(chan);
705 if (!sw_desc) {
710 xilinx_dpdma_sw_desc_set_dma_addrs(chan->xdev, sw_desc, sw_desc,
713 hw_desc = &sw_desc->hw;
725 list_add_tail(&sw_desc->node, &tx_desc->descriptors);
828 struct xilinx_dpdma_sw_desc *sw_desc;
858 list_for_each_entry(sw_desc, &desc->descriptors, node)
859 sw_desc->hw.desc_id = desc->vdesc.tx.cookie
862 sw_desc = list_first_entry(&desc->descriptors,
865 lower_32_bits(sw_desc->dma_addr));
869 upper_32_bits(sw_desc->dma_addr)));
1073 struct xilinx_dpdma_sw_desc *sw_desc;
1087 sw_desc = list_first_entry(&pending->descriptors,
1089 if (sw_desc->hw.desc_id != desc_id) {
1092 chan->id, sw_desc->hw.desc_id, desc_id);