Lines Matching defs:val
528 #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \
530 val, cond, delay_us, timeout_us)
1307 u32 val;
1312 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1313 val & XILINX_DMA_DMASR_HALTED, 0,
1325 u32 val;
1327 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1328 val & XILINX_DMA_DMASR_IDLE, 0,
1339 u32 val;
1344 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1345 !(val & XILINX_DMA_DMASR_HALTED), 0,