Lines Matching refs:pdma
216 struct xgene_dma *pdma;
248 * @pdma: X-Gene DMA device structure reference
272 struct xgene_dma *pdma;
344 static bool is_pq_enabled(struct xgene_dma *pdma)
348 val = ioread32(pdma->csr_efuse + XGENE_SOC_JTAG1_SHADOW);
1014 struct xgene_dma *pdma = (struct xgene_dma *)id;
1018 val = ioread32(pdma->csr_dma + XGENE_DMA_INT);
1021 iowrite32(val, pdma->csr_dma + XGENE_DMA_INT);
1026 dev_err(pdma->dev,
1036 iowrite32(ring->num, ring->pdma->csr_ring + XGENE_DMA_RING_STATE);
1039 iowrite32(ring->state[i], ring->pdma->csr_ring +
1083 ring->pdma->csr_ring + XGENE_DMA_RING_ID);
1087 ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF);
1101 val = ioread32(ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE);
1103 iowrite32(val, ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE);
1112 val = ioread32(ring->pdma->csr_ring +
1115 iowrite32(val, ring->pdma->csr_ring +
1121 iowrite32(ring_id, ring->pdma->csr_ring + XGENE_DMA_RING_ID);
1123 iowrite32(0, ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF);
1129 ring->cmd_base = ring->pdma->csr_ring_cmd +
1172 dma_free_coherent(ring->pdma->dev, ring->size,
1191 ring->pdma = chan->pdma;
1193 ring->num = chan->pdma->ring_num++;
1257 static int xgene_dma_init_rings(struct xgene_dma *pdma)
1262 ret = xgene_dma_create_chan_rings(&pdma->chan[i]);
1265 xgene_dma_delete_chan_rings(&pdma->chan[j]);
1273 static void xgene_dma_enable(struct xgene_dma *pdma)
1278 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1281 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1284 static void xgene_dma_disable(struct xgene_dma *pdma)
1288 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1290 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1293 static void xgene_dma_mask_interrupts(struct xgene_dma *pdma)
1300 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1302 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1304 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1306 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1308 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1311 iowrite32(XGENE_DMA_INT_ALL_MASK, pdma->csr_dma + XGENE_DMA_INT_MASK);
1314 static void xgene_dma_unmask_interrupts(struct xgene_dma *pdma)
1321 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1323 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1325 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1327 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1329 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1333 pdma->csr_dma + XGENE_DMA_INT_MASK);
1336 static void xgene_dma_init_hw(struct xgene_dma *pdma)
1342 pdma->csr_dma + XGENE_DMA_CFG_RING_WQ_ASSOC);
1345 if (is_pq_enabled(pdma))
1347 pdma->csr_dma + XGENE_DMA_RAID6_CONT);
1349 dev_info(pdma->dev, "PQ is disabled in HW\n");
1351 xgene_dma_enable(pdma);
1352 xgene_dma_unmask_interrupts(pdma);
1355 val = ioread32(pdma->csr_dma + XGENE_DMA_IPBRR);
1358 dev_info(pdma->dev,
1364 static int xgene_dma_init_ring_mngr(struct xgene_dma *pdma)
1366 if (ioread32(pdma->csr_ring + XGENE_DMA_RING_CLKEN) &&
1367 (!ioread32(pdma->csr_ring + XGENE_DMA_RING_SRST)))
1370 iowrite32(0x3, pdma->csr_ring + XGENE_DMA_RING_CLKEN);
1371 iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_SRST);
1374 iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN);
1377 ioread32(pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN);
1382 if (ioread32(pdma->csr_ring + XGENE_DMA_RING_BLK_MEM_RDY)
1384 dev_err(pdma->dev,
1391 pdma->csr_ring + XGENE_DMA_RING_THRESLD0_SET1);
1393 pdma->csr_ring + XGENE_DMA_RING_THRESLD1_SET1);
1395 pdma->csr_ring + XGENE_DMA_RING_HYSTERESIS);
1399 pdma->csr_ring + XGENE_DMA_RING_CONFIG);
1404 static int xgene_dma_init_mem(struct xgene_dma *pdma)
1408 ret = xgene_dma_init_ring_mngr(pdma);
1413 iowrite32(0x0, pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1416 ioread32(pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1421 if (ioread32(pdma->csr_dma + XGENE_DMA_BLK_MEM_RDY)
1423 dev_err(pdma->dev,
1431 static int xgene_dma_request_irqs(struct xgene_dma *pdma)
1437 ret = devm_request_irq(pdma->dev, pdma->err_irq, xgene_dma_err_isr,
1438 0, "dma_error", pdma);
1440 dev_err(pdma->dev,
1441 "Failed to register error IRQ %d\n", pdma->err_irq);
1447 chan = &pdma->chan[i];
1455 devm_free_irq(pdma->dev, pdma->err_irq, pdma);
1458 chan = &pdma->chan[i];
1470 static void xgene_dma_free_irqs(struct xgene_dma *pdma)
1476 devm_free_irq(pdma->dev, pdma->err_irq, pdma);
1479 chan = &pdma->chan[i];
1503 is_pq_enabled(chan->pdma)) {
1507 !is_pq_enabled(chan->pdma)) {
1531 static int xgene_dma_async_register(struct xgene_dma *pdma, int id)
1533 struct xgene_dma_chan *chan = &pdma->chan[id];
1534 struct dma_device *dma_dev = &pdma->dma_dev[id];
1566 dev_info(pdma->dev,
1574 static int xgene_dma_init_async(struct xgene_dma *pdma)
1579 ret = xgene_dma_async_register(pdma, i);
1582 dma_async_device_unregister(&pdma->dma_dev[j]);
1583 tasklet_kill(&pdma->chan[j].tasklet);
1593 static void xgene_dma_async_unregister(struct xgene_dma *pdma)
1598 dma_async_device_unregister(&pdma->dma_dev[i]);
1601 static void xgene_dma_init_channels(struct xgene_dma *pdma)
1606 pdma->ring_num = XGENE_DMA_RING_NUM;
1609 chan = &pdma->chan[i];
1610 chan->dev = pdma->dev;
1611 chan->pdma = pdma;
1618 struct xgene_dma *pdma)
1630 pdma->csr_dma = devm_ioremap(&pdev->dev, res->start,
1632 if (!pdma->csr_dma) {
1644 pdma->csr_ring = devm_ioremap(&pdev->dev, res->start,
1646 if (!pdma->csr_ring) {
1658 pdma->csr_ring_cmd = devm_ioremap(&pdev->dev, res->start,
1660 if (!pdma->csr_ring_cmd) {
1665 pdma->csr_ring_cmd += XGENE_DMA_RING_CMD_SM_OFFSET;
1674 pdma->csr_efuse = devm_ioremap(&pdev->dev, res->start,
1676 if (!pdma->csr_efuse) {
1686 pdma->err_irq = irq;
1694 pdma->chan[i - 1].rx_irq = irq;
1702 struct xgene_dma *pdma;
1705 pdma = devm_kzalloc(&pdev->dev, sizeof(*pdma), GFP_KERNEL);
1706 if (!pdma)
1709 pdma->dev = &pdev->dev;
1710 platform_set_drvdata(pdev, pdma);
1712 ret = xgene_dma_get_resources(pdev, pdma);
1716 pdma->clk = devm_clk_get(&pdev->dev, NULL);
1717 if (IS_ERR(pdma->clk) && !ACPI_COMPANION(&pdev->dev)) {
1719 return PTR_ERR(pdma->clk);
1723 if (!IS_ERR(pdma->clk)) {
1724 ret = clk_prepare_enable(pdma->clk);
1732 ret = xgene_dma_init_mem(pdma);
1743 xgene_dma_init_channels(pdma);
1746 ret = xgene_dma_init_rings(pdma);
1750 ret = xgene_dma_request_irqs(pdma);
1755 xgene_dma_init_hw(pdma);
1758 ret = xgene_dma_init_async(pdma);
1765 xgene_dma_free_irqs(pdma);
1769 xgene_dma_delete_chan_rings(&pdma->chan[i]);
1773 if (!IS_ERR(pdma->clk))
1774 clk_disable_unprepare(pdma->clk);
1781 struct xgene_dma *pdma = platform_get_drvdata(pdev);
1785 xgene_dma_async_unregister(pdma);
1788 xgene_dma_mask_interrupts(pdma);
1789 xgene_dma_disable(pdma);
1790 xgene_dma_free_irqs(pdma);
1793 chan = &pdma->chan[i];
1798 if (!IS_ERR(pdma->clk))
1799 clk_disable_unprepare(pdma->clk);