Lines Matching defs:csr_dma
295 * @csr_dma: base for DMA register access
307 void __iomem *csr_dma;
1018 val = ioread32(pdma->csr_dma + XGENE_DMA_INT);
1021 iowrite32(val, pdma->csr_dma + XGENE_DMA_INT);
1278 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1281 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1288 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1290 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1300 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1302 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1304 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1306 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1308 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1311 iowrite32(XGENE_DMA_INT_ALL_MASK, pdma->csr_dma + XGENE_DMA_INT_MASK);
1321 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1323 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1325 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1327 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1329 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1333 pdma->csr_dma + XGENE_DMA_INT_MASK);
1342 pdma->csr_dma + XGENE_DMA_CFG_RING_WQ_ASSOC);
1347 pdma->csr_dma + XGENE_DMA_RAID6_CONT);
1355 val = ioread32(pdma->csr_dma + XGENE_DMA_IPBRR);
1413 iowrite32(0x0, pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1416 ioread32(pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1421 if (ioread32(pdma->csr_dma + XGENE_DMA_BLK_MEM_RDY)
1630 pdma->csr_dma = devm_ioremap(&pdev->dev, res->start,
1632 if (!pdma->csr_dma) {